Channel Metal Oxide Semiconductor Research Articles

Detection and Analysis of Radiation Doses in Multiple Orbital Space during Solar Minimum

Based on orbit detection data acquired by a positive channel Metal Oxide Semiconductor (PMOS) dose detectors on FY4-A (GEO), BD3-M15 (MEO), and YH1-01A (LEO) between November 2018 and November 2022, investigations reveal variations in total dose and the mechanism of radiation dose increase within the geostationary earth orbit (GEO), medium earth orbit (MEO), and low earth orbit (LEO) during the transition from the 24th to the 25th solar cycles. It provides the radiation dose parameters for the study of the space environment from different altitude orbits, and also provides an important basis for studying the solar minimum activity and dose generation The data indicate directional disparities in radiation doses among the orbital regions, with the hierarchy being FY4-A > YH1-01A > BD3-M15. Furthermore, the results show that the total doses of FY4-A and BD3-M15 were higher than that of YH1-01A by two orders of magnitude, with BD3-M15 > FY4-A > YH1-01A. The monthly radiation dose rates of FY4-A in GEO and BD3-M15 in MEO exhibited positive correlation with their corresponding APs during the solar minimum. Notably, for FY4-A, the monthly radiation dose rate during geomagnetic disturbed periods exceeded that of the dose rate during geomagnetic quiet periods by one order of magnitude. This analysis revealed the substantial impact of geomagnetic storms and space environment disturbances on radiation doses detected by MEO and GEO orbital satellites. These perturbations, attributable to medium- and small-scale high-energy electron storms induced by reproducible coronal holes, emerged as key driving factors of the increase in radiation doses in MEO and GEO environments.

Ab initio investigations of two-dimensional carrier gas at interfaces in GaN/AlN and GaN/AlN/Al2O3 heterostructures

The formation of a two-dimensional electron gas (2DEG) at the GaN (0001)/AlN interface holds significant implications for GaN-based high-voltage and high-frequency (RF) devices. Due to the promising results provided by the addition of a thin layer of AlN in metal–oxide-semiconductor channel high-electron-mobility transistor devices, this interface can be found in both the access region and near the dielectric gate. Recent ab initio simulations shed light on the crucial role played by spontaneous and piezoelectric polarizations within polar GaN and AlN crystals in driving the formation of the 2DEG. This study explores the underlying mechanisms behind the 2DEG formation and investigates the impact of fixed charges and additional layers, like Al2O3, on the carrier concentration. Consistent with the literature, our findings highlight the predominant role of polarizations within III–V materials in the formation of the 2DEG. Moreover, we examine the influence of fixed charges on the AlN surface, revealing their ability to accumulate or deplete the 2DEG, while maintaining charge conservation through the emergence of a new two-dimensional charge gas on the AlN surface. Additionally, we explore the effects of incorporating a β-Al2O3 crystal layer on the GaN/AlN structure, finding that the 2DEG’s carrier density is reduced, yet not entirely eliminated, while a significant positive charge concentration at the AlN/Al2O3 interface pins the Fermi level. This comprehensive investigation contributes to our understanding of microscopic phenomena in III–V heterostructures, paving the way for future advancements and applications in power electronics.

3D to 2D perspectives - Traditional and new doping and metrology challenges at the nanoscale

In this perspectives paper we will explore the doping state-of-the-art as it evolves for 3D to 2D structures and materials, and the following impact on the metrology methods needed to characterise them. Historically, silicon devices for logic complementary metal-oxide-semiconductor (MOS) are built in bulk monocrystalline substrates. In this context bulk silicon substrates are 3D, as there is not the electrostatic confinement associated with more technologically advanced device structures. The determination of technology figures-of-merit such as sheet resistance, impurity concentration and activation profiles versus depth, and reverse bias leakage current to track crystal quality post-doping process, have been the typical methods for evaluation. Since the emergence of FinFET, gate-all-around (GAA) for logic, and layered 2D materials such as transition-metal-dichalcogenides (TMDs) for MOS channel active areas, these figures-of-merit are more awkward to extract, or simply do not apply in the usual sense. Logic devices, like MOS transistors, depend on doping processes to lower access resistance and thus drive performance, traditionally relied on ion implantation to introduce impurities to the substrate, which is a physical bombardment that damages the target material. Gentler doping processes that rely on in-diffusion are an emerging category, and most recently the concept of terminating or functionalising the (near-) surface of the semiconductor is growing in popularity, at least in research labs. Likewise, methods to characterise these require evolution to adapt to the times, from the conventional high-throughput techniques to the more exploratory, albeit lower throughput, methods. Metrology relies upon high-sensitivity, large dynamic range of detection, spatial resolution, as well as time- and cost-efficient sample preparation and post-analysis data interpretation. Driven primarily by the continued development of novel, scaled-down, truly unique device architectures and the introduction of novel materials in the nano-fabrication technology, the portfolio of dopant characterisation methods is unremittingly enlarging its numbers. Herein, we focus our discussion onto dopant profiling for fin and nanowire FETs, and relate these to analysis of test vehicles such as arrays of fin structures with varying dimensions. Although reports detailing correlative use of the dopant characterisation methods are only a few, we present examples that provided unique new information, in absence of which the overall description of the dopant process is inconclusive and, in some cases, misleading.

A novel double RESURF SOI-LIGBT with dynamic avalanche immunity and low losses

A novel, trench gates, double reduced surface field, lateral insulated gate bipolar transistor based on silicon-on-insulator (SOI-LIGBT) is proposed and investigated. A p-top layer connected to the emitter via two series diodes and n-rings surrounding the bottom of trench gates are used to reduce the on-state voltage drop (V CE(sat)) and turn-off loss (E off). A deep trench with a p-ring is introduced to form a gate-drain shorted positive channel metal oxide semiconductor, which can automatically raise the potential of the p-ring during turn-off so as to enhance the dynamic avalanche immunity. Besides, the deep trench with a p-ring can shield the high electric field from n-rings at the blocking state, which avoids the breakdown of n-rings. Simulation results indicate that the proposed LIGBT can be safely turned off even under a bus voltage equal to the breakdown voltage (V B), and V CE(sat) under E off = 1 mJ cm−2 can be 24% lower than that of the conventional LIGBT.

Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits

Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor (CMOS)-based Very Large-Scale Integration (VLSI) circuit designs. Positive Channel Metal Oxide Semiconductor (PMOS) has been replaced by Negative Channel Metal Oxide Semiconductor (NMOS) in recent years, with low dimension-switching changes in order to shape the mirror of voltage comparator. NMOS is used to reduce stacking leakage as well as total exchange. Domino Logic Circuit is a powerful and versatile digital programmer that gained popularity in recent years. In this study regarding Adaptive Sub Threshold Voltage Level Control Problem, the researchers intend to solve the contention issues, reduce power dissipation, and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control (ASVLC)-based domino circuit. The efficiency and effectiveness of the domino circuit are demonstrated through simulation results. The suggested system makes use of high-speed broad fan-gate circuits, occupies minimum space, and consumes meagre amount of power. The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V, frequency of 100 MHz, and an operating temperature of 27°C with 64 input OR gates. As per the simulation results, the suggested Domino Gate reduced the power dissipation by 17.58 percent and improved the noise immunity by 1.21 times in comparison with standard domino logic circuits.

Fast protection strategy for monopole grounding fault of low-voltage DC microgrid

• This paper presents a low-voltage DC microgrid ground short-circuit fault protection system based on positive channel metal oxide semiconductor (PMOS). • In case of ground short-circuit fault in DC microgrid, the coupling energy of the short-circuit current makes the PMOS to be turned off reliably. • In addition, because the primary inductance of the transformer plays a certain current limiting role, the turn-off current of PMOS will not increase sharply. Low voltage DC microgrid has attracted more and more attention in smart grid with its advantages such as low network loss, large transmission capacity and easy direct access to distributed power supply. However, compared with the traditional AC microgrid, the DC microgrid lacks inertia support and the fault develops rapidly, which makes the existing short-circuit current protection technology difficult to meet the requirements of accurate and efficient troubleshooting. Therefore, this paper presents a low-voltage DC microgrid ground short-circuit fault protection system based on positive channel metal oxide semiconductor (PMOS) self-powering DC solid-state circuit breaker protection elements, and verifies the feasibility and effectiveness of the protection system through simulation experiments. The experimental results show that the proposed protection system based on solid state circuit breaker will not affect the voltage of DC microgrid when it is normally on; In case of ground short-circuit fault in DC microgrid, the coupling energy of the short-circuit current makes the PMOS to be turned off reliably. In addition, because the primary inductance of the transformer plays a certain current limiting role, the turn-off current of PMOS will not increase sharply. The solid-state circuit breaker can effectively block the fault without a buffer circuit, which has a good application prospect.

DC Microgrid Protection System Based on Positive Channel Metal Oxide Semiconductor

DC microgrid has received extensive attention and research because of its natural advantages of improving the consumption efficiency of distributed power sources, and in line with the development trend of clean environment and intelligent operation of power grids in the future. However, short-circuit fault protection of DC microgrid is a major challenge for the development of microgrid. Therefore, the author proposes a DC solid-state circuit breaker with a positive channel metal oxide semiconductor as the main switch, and through simulation, it is verified that this solid-state circuit breaker is feasible. The experimental results show that when the proposed solid-state circuit breaker is normally turned on, the positive channel metal oxide semiconductor is completely turned on, which has no effect on the power flow in the DC microgrid; when a short-circuit fault occurs in the DC microgrid system, the short-circuit current is used to couple the energy, the positive channel metal oxide semiconductor is reliably turned off. The stability and reliability of the system are improved, and it can be applied to the short-circuit protection of the DC microgrid, and has a good application prospect.

CMOS Transistors Based First-Order Voltage-Mode All-Pass Filter with Tunable Transformation Possibility

In this paper, a novel complementary metal-oxide semiconductor (CMOS) transistors based first-order voltage-mode all-pass filter is proposed. The filter circuit employs six metal-oxide semiconductor (MOS) transistors and minimal number of passive components, i.e., a resistor and a capacitor. The core of the proposed filter is a CMOS inverting amplifier with unity gain. The proposed circuit exhibits some attractive features such as compact design, high input impedance and ability to provide non-inverting and inverting all-pass responses simultaneously. Additionally, it does not require any kind of passive element matching constraints. Furthermore, by replacing the passive resistor with an active negative channel metal-oxide semiconductor (NMOS) transistor, the proposed filter is enriched with the much-desired feature of tunability. The theoretical behavior is tested and demonstrated by carrying SPICE simulations using TSMC 0.18[Formula: see text][Formula: see text]m level-7 CMOS process parameters.

Small-Signal Processing Low-Overhead Operational Amplifier for delta-Sigma ADC

Aiming at the fully differential (FD) sensing and high-precision small-signal output characteristics of micro-electromechanical systems (MEMS) gyroscopes, a low area overhead, high-gain, medium-speed, FD operation amplifier (Op-Amp) is designed for building a small-signal processing delta-Sigma analog-to-digital converter (ADC). The Op-Amp is a two-stage cascade structure, which combines folded cascade (FC) and gain-boosted technology to make the low frequency gain up to 129 dB, to meet the high-precision requirements of 18-bit delta-Sigma ADC. The first stage is FC gain-boosted structure, which uses a small bias current to achieve high-gain and low area overhead. In order to reduce the input noise, process smaller signals, the input pair adopts positive channel Metal–Oxide–Semiconductor (PMOS). The second-stage uses a large bias current to achieve a high unity gain bandwidth (UGB). Under the premise that the tail current source of the first stage is PMOS, in order to reduce the area overhead, abandoning the traditional common source (CS) structure of negative channel Metal–Oxide–Semiconductor (NMOS) input and PMOS as the current mirror load, adopting a new CS structure that PMOS input and NMOS used as independent bias current source. In this structure, the large overdrive voltage significantly reduces the size of transistors and greatly reduces the area overhead. The Op-Amp was implemented in SMIC 0.18 μm BCD process, 5 V supply voltage. Its post-layout simulation achieved a low-frequency gain of 129 dB, a UGB of 35 MHz and a phase margin (PM) of 62° for a load capacitance of 2 pF. Output voltage swings are ±3.71 V and including common mode feedback (CMFB), bias voltage generating circuit and filter capacitor, the area of Op-Amp is 167.162 μm × 200.82 μm. Behavioral-level verification shows that the designed Op-Amp meets the requirements of high-precision delta-Sigma ADCs.

Investigation of degradation mechanism after negative bias temperature stress in Si/SiGe channel metal–oxide–semiconductor capacitors induced by hydrogen diffusion

In this research, based on I–V and C–V measurement at different temperatures, the interface defect density in the device with the Si/SiGe channel was discussed. In addition, negative bias temperature instability (NBTI) is also studied. In previous research, most of the flat-band voltage (V FB) shifts during NBTI stress was attributed to hole injection. In this article, however, the release of atomic hydrogen from the Si–H bonds at the SiO2/Si interface and at the SiGe interface produces a fixed oxide charge, which causes V FB shifts which vary with material.

Process Development of Dislocation-Free SiGe P-Channel in FinFET Technology

SiGe channel metal oxide semiconductor field effect transistor (MOSFET) became a choice of material as a performance booster in leading edge logic technologies. In this study, we demonstrate integration solutions for dual fin formation (Si for nFET, SiGe for pFET) using buried SiGe channel approach on 300 mm Si wafer. Plasma-induced damage (PID) layer, which thickness ranges from 0.5 nm to 2.5 nm, was observed after Si trench (p-trench) etch for SiGe EPI growth. This PID inorganic layer leads to SiGe dislocation defect. And careful sequencing and optimization of oxidation and wet removal steps were able to realize defect-free SiGe EPI channel along with a thin buffer SiGe layer. Besides, margin assessment of p-trench based buried SiGe approach was also presented in this study. Moreover, dual fin etch was demonstrated via inductively coupled plasma (ICP) using ALD-like function. The depth loading between SiGe and Si Fin was tunable via varying repeated cycles of advanced pulsing step, and less than 40 A of depth loading can be achieved. The progress reported represents a major leap for SiGe channel integration and paves the way for massive production.

Process Development of Dislocation-Free SiGe P-Channel in FinFET Technology

SiGe channel metal oxide semiconductor field effect transistor (MOSFET) became a choice of material as a performance booster in leading edge logic technologies. In this study, we demonstrate integration solutions for dual Fin formation (Si for nFET, SiGe for pFET) using buried SiGe channel approach on 300 mm Si wafer. Plasma-induced damage (PID) layer, which thickness ranges from 0.5 nm to 2.5 nm, was observed after Si trench (p-trench) etch for SiGe EPI growth. This PID inorganic layer leads to SiGe dislocation defect. And careful sequencing and optimization of oxidation and wet removal steps were able to realize defect-free SiGe EPI channel along with a thin buffer SiGe layer. Besides, margin assessment of p-trench based buried SiGe approach was also presented in this study. Moreover, dual Fin etch was demonstrated via inductively coupled plasma (ICP) using ALD-like function. The depth loading between SiGe and Si Fin was tunable via varying repeated cycles of advanced pulsing step, and less than 40 A of depth loading can be achieved. The progress reported represents a major leap for SiGe channel integration and paves the way for massive production.

Reduction of Source/Drain Series Resistance in Fin Channel MOSFETs Using Selective Oxidation Technique

A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 μA/μm, 0.33 V, 13.5 μS, 76.4 μS, 78 mV/dec, and 62 mV/V, respectively.

Current-to-transconductance ratio technique for simultaneous extraction of threshold voltage and parasitic resistances in MOSFETs

In this work, a current-to-transconductance ratio technique is proposed for simultaneous extraction of the threshold voltage (VT) and parasitic source (RS) and drain (RD) resistances in short channel metal–oxide–semiconductor field-effect transistors (MOSFETs). The proposed technique allows simultaneous extraction of RS, RD, and VT in any single MOSFET with the channel length modulation (CLM) and the structural asymmetry. The proposed method is experimentally verified through Si MOSFETs with intentional asymmetry by connecting an external resistor (Rext) to the source terminal. We experimentally confirmed that extracted RS, RD, and VT are independent of the drain bias (VDS) and intentional Rext employed for the asymmetry. We also compared the results with previously reported techniques.

Ultra‐low power voltage reference with 40 μA maximum load current for passive sensor systems

An ultra-low power, low temperature coefficient voltage reference generator used for nanowatt-level passive sensor systems is presented. The voltage reference configuration, based on a voltage reference generating circuit embedded in the feedback loop, realises an average reference voltage (VREF) of 837.2 mV and 40 μA maximum load current. The temperature coefficient of VREF is compensated by a saturated diode-connected the positive channel Metal Oxide Semiconductor (PMOS) and a proportional to absolute temperature current. For supply voltages ranging from 0.86 to 3 V, this proposed voltage reference simulated in 55 nm a Complementary Metal Oxide Semiconductor (CMOS) process consumes an average current of 10 nA at room temperature and achieves a minimum temperature coefficient of 8.1 ppm/°C from −40°C to 125°C. The mean line sensitivity is 0.17%/V and the coefficient of variation is 2.1%.

Effects of Total Dose Radiation on Single Event Effect of the Uniaxial Strained Si Nano NMOSFET

The effect of total dose radiation on the single event effect of uniaxial strained Si Nano channel metal oxide semiconductor field effect transistor (NMOSFET) was studied by TCAD simulation. By comparing the experimental results, the TCAD simulation model of the 50 nm strained Si NMOS device is established. The model is used to simulate the off-state single event effect (V ds = 0.05) of NMOSFET under the total dose radiation. The results show that total dose radiation increases the body potential of NMOSFET devices and intensifies the single event transient process of NMOSFET devices. The transient current increases by 4.88% and the drain charge increases by 29.15% under the total dose of 2KGy, which indicates that the effect of total dose radiation on the single event effect is the main factor affecting the collection of drain charge. Therefore, the experimental results and the established model provide good reference for the study of irradiation reliability of the uniaxial strained Si Nano NMOSFET and the application of strained integrated circuits.

Third Quadrant Conduction Loss of 1.2–10 kV SiC MOSFETs: Impact of Gate Bias Control

The third quadrant (3rd-quad) conduction of power MOSFETs involves competing current sharing between the metal-oxide-semiconductor (MOS) channel and the body diode controlled by the gate bias (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ). For 1.2 kV SiC planar MOSFETs, it is well known that a positive V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> higher than the threshold voltage enables parallel conduction through both channels, which reduces the 3rd-quad voltage drop and conduction loss. This work, for the first time, unveils that this fact does not hold for higher voltage (e.g., 3.3 kV and 10 kV) SiC planar MOSFETs. By combining the static characterization, simulation, and modeling, it is revealed that, once the MOS channel turns on, the body diode in high-voltage MOSFETs turns on at a source-to-drain voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> ) much higher than the built-in potential of the PN junction. In 10 kV SiC MOSFETs, the body diode does not turn on over the entire practical V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</sub> range if the MOS channel is on. As a result, the positive V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> leads to completely unipolar conduction, which could induce a higher voltage drop than the bipolar body diode at high temperatures. A buck converter based on a 10 kV SiC MOSFET half-bridge module was built and tested, which validated that a negative V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> control provides the smallest 3rd-quad voltage drop and conduction loss at high temperatures. Finally, based on the revealed physics for planar MOSFETs, the optimal V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> control for the 3rd-quad conduction in trench MOSFETs is discussed. These results provide critical device understandings of 1.2-10 kV SiC MOSFETs and important application guidelines for 10 kV SiC MOSFETs.

Influence of Structural Parameters on the Behavior of an Asymmetric Linearly Graded Workfunction Trapezoidal Gate SOI MOSFET

This paper presents a dual metal trapezoidal recessed channel metal oxide semiconductor field effect transistor (MOSFET) embedded with asymmetric stack gate with linearly graded metal work-function technique to improve the carrier transport efficiency and device switching performance. The analytical model for the proposed asymmetric-linearly graded trapezoidal gate (ASY–LGTG) silicon on insulator (SOI) MOSFET has been developed considering parabolic approximation of 2-D Poisson’s equation. The threshold voltage of the device is extracted using minimum surface potential. The simulation work has been carried out using a Silvaco TCAD tool to validate the results of the analytical model. This grooved structure exhibits the corner effect, which plays a dynamic role in the improvement of the device performance. However, the impact of the corner effect can be controlled by the groove corner angle and doping concentration. We have also investigated the impact of different structural parameters such as negative junction depth (NJD), corner angle, substrate doping and stack gate features (upper oxide permittivity and oxide thickness ratio) on the performance of minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage and device switching characteristics.

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO2

A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO₂

Normally-off recessed-gate AlGaN/GaN MOS-HFETs with plasma enhanced atomic layer deposited AlOxNy gate insulator

We developed a high-quality plasma enhanced atomic layer deposited (PEALD) aluminum oxynitride (AlOxNy) process for the metal-oxide-semiconductor (MOS) gate insulator of fully-recessed-gate AlGaN/GaN-on-Si MOS-heterojunction field-effect transistors (MOS-HFETs). It was found that the cyclic nitrogen incorporation into aluminum oxide (Al2O3) during PEALD process improved the conduction band offset at GaN interface resulting in higher forward breakdown field strength, which also contributed to suppressed trapping effects under forward gate bias stress. Improved interface characteristics, which resulted from suppressed surface oxidation, led to significant improvement of threshold voltage stability. A low threshold voltage hysteresis of 180 mV at maximum gate sweep voltage of 10 V was obtained with AlOxNy gate insulator. The MOS channel mobility was also improved to 235 cm2 V−1 s−1. The fabricated fully-recessed-gate AlGaN/GaN-on-Si MOS-HFET with PEALD AlOxNy gate insulator exhibited excellent overall performances such as a threshold voltage of 3.2 V, a maximum drain current density of 481 mA mm−1, an on/off current ratio of ∼1010, an ON-resistance of 12 mΩ mm, and a breakdown voltage of 1050 V.