Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits

Abstract

Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor (CMOS)-based Very Large-Scale Integration (VLSI) circuit designs. Positive Channel Metal Oxide Semiconductor (PMOS) has been replaced by Negative Channel Metal Oxide Semiconductor (NMOS) in recent years, with low dimension-switching changes in order to shape the mirror of voltage comparator. NMOS is used to reduce stacking leakage as well as total exchange. Domino Logic Circuit is a powerful and versatile digital programmer that gained popularity in recent years. In this study regarding Adaptive Sub Threshold Voltage Level Control Problem, the researchers intend to solve the contention issues, reduce power dissipation, and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control (ASVLC)-based domino circuit. The efficiency and effectiveness of the domino circuit are demonstrated through simulation results. The suggested system makes use of high-speed broad fan-gate circuits, occupies minimum space, and consumes meagre amount of power. The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V, frequency of 100 MHz, and an operating temperature of 27°C with 64 input OR gates. As per the simulation results, the suggested Domino Gate reduced the power dissipation by 17.58 percent and improved the noise immunity by 1.21 times in comparison with standard domino logic circuits.