A NOVEL DOMINO TECHNIQUE TO REDUCE POWER DISSIPATION AND DELAY VARIATIONS

Abstract

In this work, a new composition of domino logic circuit with reduced power dissipation and delay variations has been proposed. In this circuit both evaluation and keeper circuitries have been modified to minimize power dissipation and improve noise immunity respectively without affecting delay. Basically in keeper setup, two keeper transistors in series have been utilized instead of one as in standard domino logic circuit. While in evaluation setup a transistor in diode configuration has been utilized along with a mirror transistor and an evaluation transistor. This dynamic circuit can be used for designing high fan-in gates which are the basic building block for high-speed microprocessors. Simulation work is realized using cadence virtuoso tool in 180nm technology node, results show that the proposed domino circuit gives around 81.1 % & 22.5% reduction in power dissipation and 56% & 1.9% improvement in noise immunity than conventional domino without footer transistor and diode footed domino circuit respectively.