Channel Layer Thickness Research Articles

Effects of spacer layer thickness in InAlN/GaN double-channel HEMTs

In this paper, the impact of upper channel layer thickness on the electrical characteristics and hysteresis behavior of double-channel InAlN/GaN HEMTs were investigated. The devices with an upper channel layer thickness of 20 nm exhibit higher output current and lower R on compared to devices with a thickness of 10/6 nm. This is attributed to the higher sheet carrier density and the reduced scattering. However, a 20 nm thickness of the upper channel layer in HEMT exhibits hysteresis phenomena in its electrical characteristics. For this hysteresis phenomenon, capacitance measurements and TEM characterization indicate that it is caused by dislocations in the lower barrier layer under the gate. A thicker upper channel layer is beneficial to increasing the output current of the device but leads to degradation of the lower InAlN barrier layer, resulting in hysteresis. This study provides an optimized solution for the growth and device fabrication of double-channel InAlN materials.

A Closed-Form Model for 2-DEG Charge and Surface Potential in N-Polar Gallium Nitride Heterostructures

A closed-form model to calculate the 2-D electron gas (2-DEG) charge density and surface potential in an N-polar GaN/AlGaN heterostructure is presented. The proposed model is developed from the solution of Schrödinger’s equation for a finite triangular potential well. Asymptotic expressions of Airy functions are used to compute an initial value of subband energy. A new, unified expression to update the surface potential due to Poisson’s equation is presented. The modified Fang–Howard (M.F.H.) function is then employed to develop a closed-form correction to the subband energy using first-order perturbation theory. No fitting parameters are used. The results from our model are validated with numerical data for a wide range of bias conditions, channel layer thickness, and spacer layer mole fraction. Finally, the gate capacitance of the heterostructure is evaluated using automatic differentiation and validated against experimental data.

The study of N-polar GaN/InAlN MOS-HEMT and T-gate HEMT biosensors

The sensing performance of N-polar GaN/InAlN MOS-HEMT biosensors for neutral biomolecules was investigated and compared with the Ga-polar MOS-HEMT and N-polar T-gate HEMT by numerical simulation. The results indicate that the N-polar GaN/InAlN MOS-HEMT biosensor has higher sensing sensitivity than the Ga-polar MOS-HEMT and N-polar T-gate HEMT biosensors. Furtherly, to improve the sensing performance of N-polar MOS-HEMT, the influence of cavity dimensions, GaN channel layer thickness, and InAlN back barrier layer thickness on device performance was investigated. It is demonstrated that the sensitivity of the biosensor increases as the cavity height decreases and the cavity length increases. Therefore, the sensing performance of the N-polar MOS-HEMT device will be enhanced by thinning the GaN channel layer thickness or increasing the InAlN back barrier thickness, which can be mainly attributed to the variation of the energy band structure and two-dimensional electron gas concentration in the HEMT heterostructure. Finally, the highest sensitivity can be obtained for the N-polar MOS-HEMT with 6 nm-thick GaN channel layer, 30 nm-thick InAlN back barrier layer, and two 0.9 μm-long and 5 nm-high cavities. This work provides structural optimal design guidance for the N-polar HEMT biosensor.

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

AbstractAn analytical drain current model for double gate junctionless accumulation mode negative capacitance field effect transistor (DG‐JAM‐NC‐FET) has been developed, combining the merits of junctionless accumulation mode and negative capacitance effect such as fabrication feasibility, low power dissipation, and reduced degradation in mobility. The novelty manifested in our work is because of the incorporation of the JAM structure in ferroelectric‐based negative capacitance FET. The benefit of JAM over existing FETs is that it combines the benefits of the junctionless transistor (JLT) and conventional FETs. It avoids excessive parasitic resistance due to stronger doping in the source and drain areas, resulting in higher conductivity and better characteristics than JLT. An analytical surface potential and threshold voltage have been developed using Poisson's equation and Landau Khalatnikov's (L‐K) equation. The drain current is then determined by integrating the mobile charge using the Pao–Sah integral. Various critical parameters such as surface potential, gain, capacitance, mobile charge density, drain current, threshold voltage, subthreshold swing, transconductance, and the switching ratio have been assessed extensively by varying ferroelectric layer and channel layer thicknesses, respectively. The ON current increases with the increase in ferroelectric thickness due to the voltage amplification given by the ferroelectric layer, and the switching curve gets steeper. The analytical modeling is done in MATLAB, and its comparison is made with the TCAD numerical simulation. The obtained analytical results and the numerical simulation results correspond well.

Improving Gas Diffusion in Solid Oxide Cells Through Laser-Ablated Electrode Supports

Improving solid oxide cell power density will enable cheaper commercial-scale SOFCs and SOECs. In Ni-YSZ electrode-supported cells, gas diffusion through the electrode support layer can be a major limitation at high H2 or H2O utilization and high temperature. Conventional methods of improving diffusion through the electrode support include increasing the support porosity and reducing the support thickness, but these can reduce the cell’s structural integrity. Freeze casting1 and 3D printing2 have also been explored to enhance diffusion. Here we explore cells in which the Ni-YSZ supports have macroscopic channels, produced by laser ablation, that reduce the average gas diffusion length.To test the difference in mass transport through patterned and pristine electrode supports, symmetric electrode-supported Ni-YSZ cells are patterned on one side, which enables comparison of the electrochemical performance of two otherwise identical electrodes (Figure 1a). Cells with varying pattern geometry, pore geometries, Ni/YSZ ratios, and Ni-YSZ particle sizes were created to fully understand how the support layer microstructure and macrostructure affects the cell performance. Patterned and pristine cells were tested together at three temperatures (600C, 700C, and 800C) in a 97%H2:3%H2O environment, chosen to produce a clear gas diffusion limitation in H2O electrolysis. j-V sweeps and electrochemical impedance spectroscopy (EIS) were carried out on each cell at each test condition, and the microstructure of patterned and control supports was characterized through SEM imaging.Upon removing the ohmic portion and fitting the j-V data to Equation 1 (see Figure 1), patterned electrodes consistently demonstrated higher limiting current density and lower mass transport losses than the control (Figure 1c-d). Three-point-bend mechanical testing revealed that the mean flexural fracture strengths of pristine cells and patterned cells are 36.0 ± 11.4 MPa and 33.0 ± 8.9 MPa respectively.Combining the equations for limiting current density with diffusion in a system with prismatic channels, we determined the ratio of the limiting current density for a patterned and pristine electrode using Equation 2 (see Figure). For the cell data shown in Figures 1c-1d, we expect an average 33% increase (with a standard deviation of 3.5%) in limiting current density based on microscopy measurements of channel and support layer thicknesses. In 1c, we see that the limiting current density of the patterned electrode is 32% higher than the pristine electrode, which matches our expectation. Furthermore, the Nyquist plot in Figure 1d demonstrates that patterned symmetric cells have similar impedance to pristine cells in the high-frequency regime with less impedance in the low-frequency regime, which is consistent with our expectations that the patterned cells have reduced mass transport losses with similar ohmic and activation losses. These j-V and EIS results suggest that macroscopic support patterning is a promising method for improving performance without compromising structural integrity. Figure 1: a) Ni-YSZ symmetric cell cross-section, laser-patterned with 600 µ m by 600 µ m channels and 200 µ m channel spacing. b) Comparison of the flexural fracture strength for pristine and patterned cells, under 3-point-bend testing. c) IR-free current density-voltage profiles of a patterned Ni-YSZ symmetric cell with a predicted current density improvement of 33%, at 700C in a 97%H2:3%H2O environment. Two distinct j-V responses are observed, based on whether the pristine electrode or the patterned electrode is under a cathodic bias. d) Unbiased potentiostatic EIS (1 MHz - 100 mHz) of a pristine cell versus two patterned cells at 700 C in 97%H2:3%H2O. The cells all have similar Ohmic resistances, but the impedance of the patterned cells is significantly lower in the low-frequency regime, due to the reduction in mass-transport losses. Equation 1: a is a constant, α is the transfer coefficient, j is current density, and jlim,H2O is the limiting current density for H2O diffusion. Equation 2: jlim/jlim,0 is the limiting current density ratio, A is the fraction of the cell surface that is patterned, and tc is the ratio of the channel depth to the patterned electrode thickness.

Single‐layer thin‐film transistor analysis and design

AbstractA set of direct current (DC) analytical equations is formulated for the analysis and design of a single‐layer thin‐film transistor (TFT). For a specified TFT structure, drain current is calculated as a function of drain and gate voltage (taking the source as ground) according to the Enz, Krummenacher, Vittoz (EKV) compact model. One model parameter function is required to implement this EKV‐based equation, that is, drift mobility as a function of gate voltage. Drift mobility is evaluated as a consequence of accumulation layer electrostatics assessment of the TFT structure specified. In order to implement the model, three semiconductor properties (low‐frequency (static) relative dielectric constant, free electron concentration, and maximum (no trapping) mobility), two structure properties (insulator capacitance density and TFT width‐to‐length ratio), and one physical operating parameter (temperature) must be specified. Optimal TFT mobility performance is achieved when the thickness of the semiconductor channel layer is constrained to be less than 2.22 times the channel layer Debye length such that “short‐base” TFT operation obtains. Additionally, higher mobility TFT performance is obtained by selecting a channel layer with a small electron effective mass, reducing channel layer trap density, reducing channel layer thickness, reducing the free electron concentration, and/or increasing gate capacitance density.

Vertical GaN Transistor with Semi‐Insulating Channel

Herein, vertical GaN transistors with a semi‐insulating (SI) 1.3 μm thick channel layer and C doping of 1 × 1017 cm−3 are studied. Structures are grown using a metal–organic chemical vapor deposition on conductive GaN substrates. SI GaN is sandwiched between 2.5 μm thick n‐GaN drift layer (Si doping of ≈ 1 × 1017 cm−3) and a top n‐GaN contact layer. A circular mesa region with a diameter of 180 μm is patterned using a deep dry etching. The gate contact formed on the mesa sidewall is insulated from the vertical channel using a 20 nm thick Al2O3 grown by an atomic layer deposition. Despite a robust layout, transistors transfer characteristics indicate normally off behavior if extracted from the linearly scaled current–voltage characteristics and an open channel drain current of 30 mA at the gate bias of 4 V. Achieved on/off ratio is 107 at −2 V subthreshold gate bias when the full channel depletion is reached. And, 200 ns long gate pulse characteristics show only a marginal trapping even though no post‐metallization annealing is performed. By comparing experimental results with modeling, mobility of free electrons in the channel is found to be about 45 cm2 V−1 s−1.

Dependence of process damage on GaN channel thickness in AlGaN/GaN high-electron-mobility transistors with back-barrier layers

In this study, AlGaN/GaN high-electron-mobility transistors with 65 and 38 nm channel layers and back-barrier layers were fabricated. The isolation process resulted in damage related to the thickness of the channel layer, which deteriorated properties such as sheet resistance R sh and transconductance gm. These were attributed to the surface oxidation of the AlGaN barrier, and the simulation results showed that the channel layer thickness changed the dependence of R sh on the trap level density; however, the calculated changes were smaller than the observed changes. In the range of gate lengths we produced, suppression of the short-channel effect by the back barrier layer was confirmed. However, no significant change in the channel layer thickness was observed.

Depletion- and Enhancement-Mode p-Channel MISHFET Based on GaN/AlGaN Single Heterostructures on Sapphire Substrates

We report on p-channel metal-insulator-semiconductor heterostructure field-effect transistors (MISHFET) based on p-GaN/uid-GaN/Al0.29Ga0.71N single heterostructures on sapphire substrates, grown by metalorganic vapor phase epitaxy (MOVPE). The impact of p-GaN layer removal and channel layer thickness adjustment by dry-etching on the characteristics of the MISHFET are investigated. Depending on the remaining GaN thickness (tGaN), the fabricated MISHFET show either depletion-mode (d-mode) operation with a threshold voltage Vth of 3.8 V and an on-current |ID,on| of 9.5 mA/mm (tGaN = 21 nm) or enhancement-mode (e-mode) operation with Vth of -2.3 V and |ID,on| of 1.5 mA/mm (tGaN = 12 nm). Independent of the etching depth, all devices exhibit a very low off-state drain current |ID,off| 10-8 mA/mm and a steep subthreshold swing (SS) between 80 and 89 mV/dec. Similar to n-channel devices, a Vth instability caused by charge trapping at the dielectric/semiconductor interface is found, emphasizing that careful interface engineering is required for good device performance.

Ultraviolet photodetectors based on Si-Zn-SnO thin film transistors with a stacked channel structure and a patterned NiO capping layer

Ultraviolet photodetectors (UVPDs) based on Si-Zn-SnO (SZTO) thin-film transistors (TFTs) with a stacked dual-channel layer (DCL) structure with different carrier concentration and NiO capping layer (CL) to alleviate the trade-off between dark current (I dark) and photocurrent (I ph) are reported. Experimental results show that under 275 nm irradiation, the proposed SZTO TFT UVPD with a 30 nm thick upper layer stacked on a 50 nm thick channel layer and a patterned NiO CL exhibit excellent photoresponsivity and photosensitivity up to 1672 A W−1 and 1.03 × 107 A A−1, which is about 272 and 137 times higher than conventional 30 nm thick single-channel layer SZTO TFT. These improvements are due to the use of a DCL which forms a high-low junction to reduce the effective channel thickness and increasing the space for UV illumination and the use of NiO CL lowers the I dark and causes a considerable negative threshold voltage shift under UV irradiation to significantly boost the I ph.

Scattering Analysis of AlGaN/AlN/GaN Heterostructures with Fe-Doped GaN Buffer.

The results of the study of the influence of Fe segregation into the unintentionally doped GaN channel layer in AlGaN/AlN/GaN heterostructures with Fe-doped GaN buffer layer on the electrical properties of two-dimensional electron gas are presented. A set of several samples was grown by metal-organic vapor-phase epitaxy and characterized by the van der Pauw method. The dependence of concentration and mobility of the two-dimensional electron gas on the channel layer thickness was analyzed theoretically by self-consistent solving of 1D Poisson and Schrödinger equations and scattering rate calculations within the momentum relaxation time approximation. It was found that both concentration and mobility decreases were responsible for the increase in the sheet resistance in the structures with a thinner channel layer, with a drop in mobility being not only due to ionized impurity scattering, but also due to a combined effect of weakening of screening, lower carrier energy and change in form-factors on scattering by interface roughness, dislocations and polar optical phonons.

Simulation Study on the Structure Design of p-GaN/AlGaN/GaN HEMT-Based Ultraviolet Phototransistors.

This work investigates the impacts of structural parameters on the performances of p-GaN/AlGaN/GaN HEMT-based ultraviolet (UV) phototransistors (PTs) using Silvaco Atlas. The simulation results show that a larger Al content or greater thickness for the AlGaN barrier layer can induce a higher two-dimensional electron gas (2DEG) density and produce a larger photocurrent. However, they may also lead to a larger dark current due to the incomplete depletion of the GaN channel layer. The depletion conditions with various Al contents and thicknesses of the AlGaN layer are investigated in detail, and a borderline between full depletion and incomplete depletion was drawn. An optimized structure with an Al content of 0.23 and a thickness of 14 nm is achieved for UV-PT, which exhibits a high photocurrent density of 92.11 mA/mm, a low dark current density of 7.68 × 10-10 mA/mm, and a large photo-to-dark-current ratio of over 1011 at a drain voltage of 5 V. In addition, the effects of other structural parameters, such as the thickness and hole concentration of the p-GaN layer as well as the thickness of the GaN channel layer, on the performances of the UV-PTs are also studied in this work.

(Invited) Thin-Film Transistor Accumulation-Mode Modeling

Analytical equations are developed for electrostatic assessment of accumulation-mode thin-film transistors (TFTs) so that potential, electric field, and accumulation layer free electron concentration profiles may be generated. Additionally, equations are derived for plotting TFT trap density versus surface potential, based on accurate extraction of the channel mobility as a function of gate voltage. A key factor in formulating these device physics equations is distinguishing between a ‘long-base’ or ‘short-base’ channel thickness. A ‘long-base’ (‘short-base’) channel thickness is defined to occur when the accumulation layer thickness (as calculated in the normal manner) is less than (greater than) the physical thickness of the channel layer. The electrostatic equations derived herein are applied to the analysis of two amorphous oxide semiconductor (AOS) TFTs with differing channel layers, i.e., a 40 nm amorphous indium gallium zinc oxide (a-IGZO) or a 7 nm amorphous indium zinc oxide (a-IZO). Application of these equations suggests that optimal TFT performance is obtained when the channel layer thickness is chosen to be similar to its Debye length. Estimated trap densities of these two AOS TFTs are found to be quite similar. Therefore, the superior mobility performance of the a-IZO TFT compared to the a-IGZO TFT is ascribed to the smaller effective mass of a-IZO, assuming that the maximum (no trapping) drift mobility in the channel is established by the thermally-limited diffusive mobility.

MoS2 based Thickness Engineered Tunnel field-effect transistors for RF/analog applications

In this work, a novel 2D material-based Thickness Engineered Tunnel FET (MoS2 TE-TFET) has been proposed and investigated. The impact of channel layer thickness variation on bandgap, has been used in the device to improve ION current. A comparative analysis has been done at different channel lengths like 7 nm, 10 nm, 14 nm, and 22 nm. For devices with channel length of 10 nm, the ION is enhanced up to 1 μA/μm with subthreshold slope of 11.6 mV/decade and improved ION/IOFF ratios of 1013 have been obtained. Additionally, the RF/analog performances of the device have been explored and the parameters like TFP, TGF, τ have been analyzed.

Thin-film transistor accumulation-mode modeling

Analytical equations are developed for electrostatic assessment of accumulation-mode thin-film transistors (TFTs) so that potential, electric field, and accumulation layer free electron concentration profiles may be generated. Additionally, equations are derived for plotting TFT trap density versus surface potential, based on accurate extraction of the channel mobility as a function of gate voltage. A key factor in formulating these device physics equations is distinguishing between a ‘long-base’ or ‘short-base’ channel thickness. A ‘long-base’ (‘short-base’) channel thickness is defined to occur when the accumulation layer thickness (as calculated in the normal manner) is less than (greater than) the physical thickness of the channel layer. The electrostatic equations derived herein are applied to the analysis of two amorphous oxide semiconductor (AOS) TFTs with differing channel layers, i.e., a 40 nm amorphous indium gallium zinc oxide (a-IGZO) or a 7 nm amorphous indium zinc oxide (a-IZO). Application of these equations suggests that optimal TFT performance is obtained when the channel layer thickness is chosen to be similar to its Debye length. Estimated trap densities of these two AOS TFTs are found to be quite similar. Therefore, the superior mobility performance of the a-IZO TFT compared to the a-IGZO TFT is ascribed to the smaller effective mass of a-IZO, assuming that the maximum (no trapping) drift mobility in the channel is established by the thermally-limited diffusive mobility.

Normally-off β-Ga2O3 MOSFET with an Epitaxial Drift Layer.

A normally-off β-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed using a technology computer-aided design (TCAD) device simulation, which employs an epitaxial drift layer grown on an n-type low-doped body layer. The low-doped body layer under the MOS gate enabled normally-off operation, whereas the epitaxial drift layer determined the on-resistance and breakdown characteristics. The effects of the doping concentration of each layer and thickness of the drift channel layer on the device characteristics were investigated to design a device with a breakdown voltage of 1 kV. A threshold voltage of 1.5 V and a breakdown voltage of 1 kV were achieved by an n-type body layer with a doping concentration of 1 × 1015 cm−3 and an n-type drift layer with a doping concentration of 3 × 1017 cm−3, a thickness of 150 nm, and a gate-to-drain distance of 9.5 μm; resulting in an on-resistance of 25 mΩ·cm2.

Delta‐Doped β‐(Al0.17Ga0.83)2O3/Ga2O3 Double‐Channel Heterostructure MODFETs

Herein, in delta‐doped β‐(AlxGa1–x)2O3/β‐Ga2O3 heterostructures, the 2D electron gas (2DEG) density is mainly limited by the low conduction‐band offset at the heterointerface. Double‐channel heterostructures may be a candidate solution for enhancing the 2DEG density in these heterostructures. In this study, the output characteristics, transfer, transconductance, and off‐state current characteristics of delta‐doped β‐(Al0.17Ga0.83)2O3/β‐Ga2O3 double‐channel heterostructure modulation‐doped field‐effect transistors (MODFETs), including the effects of an ultrathin spacer layer and a back‐barrier layer, are numerically evaluated. The electrical characteristics of the proposed double‐channel heterostructure MODFET are compared with those of a single‐channel heterostructure MODFET. The proposed double‐channel heterostructure MODFET shows a maximum drain current of 133.7 mA mm−1 and a g m peak of 40 mS mm−1, which are higher than those in the single‐channel case. The calculated threshold voltage is −3.45 V. The dependence of the Si δ‐doping density in the second barrier and channel layer thickness on the electrical characteristics of the proposed device is evaluated and discussed. A β‐(Al0.17Ga0.83)2O3/β‐Ga2O3 superlattice back‐barrier structure is also implemented in delta‐doped β‐Ga2O3‐based heterostructure MODFETs to improve their off‐state characteristics for the first time.

Electron mobility distribution in FD-SOI MOSFETs using a NEGF-Poisson approach

Modern electronic devices consist of several semiconductor layers where each layer exhibits unique carrier transport properties that can be represented by a unique mobility characteristic. To date, the mobility spectrum analysis technique is the main approach that has been developed and applied to the analysis of conductivity mechanisms of multi-carrier semiconductor structures and devices. Currently, there are no theoretical calculations of the mobility distribution in semiconductor structures or devices and specifically in MOSFET devices. In this article, we present a theoretical study of the electron mobility distribution in planar fully-depleted silicon-on-insulator (FD-SOI) transistors employing quantum mechanical modelling. The simulation results indicate that electronic transport in the 10 nm thick Si channel layer at room-temperature is due to two distinct and well-defined electron species for channel length varying from 50 nm to 200 nm. The two electron mobility distributions provide clear evidence of sub-band modulated transport in 10-nm thick Si planar FD-SOI MOSFETs that are associated with primed and non-primed valleys of silicon. The potential of the top gate electrode has been modulated, and thus only the top channel inversion-layer electron population transport parameters have been investigated employing self-consistent non-equilibrium Green’s function (NEGF)–Poisson numerical calculations. The numerical framework presented can be used to interpret experimental results obtained by magnetic-field dependent geometrical magnetoresistance measurements and mobility spectrum analysis, and provides greater insight into electron mobility distributions in nanostructured FET devices.

Multi-Segment TFT Compact Model for THz Applications.

We present an update of the Rensselaer Polytechnic Institute (RPI) thin-film transistor (TFT) compact model. The updated model implemented in Simulation Program with Integrated Circuit Emphasis (SPICE) accounts for the gate voltage-dependent channel layer thickness, enables the accurate description of the direct current (DC) characteristics, and uses channel segmentation to allow for terahertz (THz) frequency simulations. The model introduces two subthreshold ideality factors to describe the control of the gate voltage on the channel layer and its effect on the drain-to-source current and the channel capacitance. The calculated field distribution in the channel is used to evaluate the channel segment parameters including the segment impedance, kinetic inductance, and gate-to-segment capacitances. Our approach reproduces the conventional RPI TFT model at low frequencies, fits the measured current–voltage characteristics with sufficient accuracy, and extends the RPI TFT model applications into the THz frequency range. Our calculations show that a single TFT or complementary TFTs could efficiently detect the sub-terahertz and terahertz radiation.

Environmentally and Electrically Stable Sol–Gel-Deposited SnO2 Thin-Film Transistors with Controlled Passivation Layer Diffusion Penetration Depth That Minimizes Mobility Degradation

This study examines the effect of the annealing time of the Y2O3 passivation layer on the electrical performances and bias stabilities of sol-gel-deposited SnO2 thin-film transistors (TFTs). The environmental stabilities of SnO2 TFTs were examined. After optimizing the Y2O3 passivation layers in SnO2 TFTs, the field-effect mobility was 7.59 cm2/V•s, the VTH was 9.16 V, the subthreshold swing (SS) was 0.88 V/decade, and the on/off-current ratio was approximately 1 × 108. VTH shifts were only -0.18 and +0.06 V under negative and positive bias stresses, respectively. The SnO2 channel layer thickness and oxygen-vacancy concentration in SnO2, which determine the carrier concentration, were successfully tuned by controlling the annealing time of the Y2O3 passivation layers. An extremely thin Y2O3 passivation layer effectively blocked external molecules, thus affecting the device performance. The electrical performance was maximized in SnO2 TFTs using a 15 min-annealed Y2O3 passivation layer. In this TFT, the field-effect mobility was maximally retained and the bias and environmental stabilities were sustained over 90 days of air exposure.