Channel Hot Electron Injection Research Articles

Design of Wireless Multiple Gases Complementary Architecture Sensors Based on SnSe2 and PtSe2 Layered Films and Oscillating Circuits

AbstractOwing to the increasing demand for monitoring harmful toxic gases using small‐sized low‐power‐consumption gas sensors, a room‐temperature wireless complimentary gas sensor incorporating layered materials is proposed and demonstrated. The compact design allows the sensing module to be installed under all conditions and facilitates multiple detections of toxic gas. Highly chemical‐resistance‐sensitive materials based on n‐type SnSe2 and p‐type PtSe2 layered materials prepared by the plasma‐assisted chemical vapor reaction (PACVR) method at low temperatures are integrated with an oscillation circuit and antenna fabricated by a 28‐nm CMOS high‐k metal gate logic process to achieve dense, low‐powered, and wireless characteristics. By pairing n‐ and p‐type layered semiconductors, the gas sensors feature less influence from the surroundings, such as temperature and humidity, and enhance sensitivity to the target gas simultaneously. The wireless sensing detection method enables a sensor to make signal reception more convenient. Furthermore, a wireless gas sensor with self‐converging calibration using the advantage of a floating‐gate (FG) transistor to control the charge quantity by shifting the threshold voltage (Vth) of each transistor via the channel hot electron injection effect, which helps to reduce the impact of process variations, minimizing readout errors, is proposed.

Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance

With the rapid development of machine learning, the demand for high-efficient computing becomes more and more urgent. To break the bottleneck of the traditional Von Neumann architecture, computing-in-memory (CIM) has attracted increasing attention in recent years. In this work, to provide a feasible CIM solution for the large-scale neural networks (NN) requiring continuous weight updating in online training, a flash-based computing-in-memory with high endurance (109 cycles) and ultra-fast programming speed is investigated. On the one hand, the proposed programming scheme of channel hot electron injection (CHEI) and hot hole injection (HHI) demonstrate high linearity, symmetric potentiation, and a depression process, which help to improve the training speed and accuracy. On the other hand, the low-damage programming scheme and memory window (MW) optimizations can suppress cell degradation effectively with improved computing accuracy. Even after 109 cycles, the leakage current (I off) of cells remains sub-10pA, ensuring the large-scale computing ability of memory. Further characterizations are done on read disturb to demonstrate its robust reliabilities. By processing CIFAR-10 tasks, it is evident that ~90% accuracy can be achieved after 109 cycles in both ResNet50 and VGG16 NN. Our results suggest that flash-based CIM has great potential to overcome the limitations of traditional Von Neumann architectures and enable high-performance NN online training, which pave the way for further development of artificial intelligence (AI) accelerators.

Characterization of trap evolution in GaN-based HEMTs under pulsed stress

In this paper, the evolution of traps in GaN-based high-electron-mobility transistors under pulsed thermal stress and the combined effect of thermal stress and electrical stress are studied. By applying impulse stresses of different powers to the device, collecting transient current response curves, and accurately extracting the time constant and absolute peak changes of the traps by employing the Bayesian inverse convolution theory time constant spectral technique, we analyzed the evolution of the traps under the action of impulse stress and clarified the influence and degradation mechanism of the thermal stress, as well as the combined action of thermal stress and electrical stress, on the evolution of traps. The results show that under pulsed stress, the decrease in electron mobility with increasing temperature leads to a decrease in device drain current, and the degradation of the device is exacerbated owing to channel hot-electron injection.

New Erratic Program Disturbance Mechanism of 2T-SONOS Embedded Nonvolatile Memory

We developed a 32 kB embedded nonvolatile memory (NVM) intellectual property (IP) using 2T-SONOS cells. Although SONOS cells possess intrinsic defect immunity, we discovered abnormal memory cell failure during the probe test of the IP. The major failed items are checkerboard (CKBD), inverse CKBD, and gate-with-source (G-S) disturbance at the erased state. The threshold voltage distributions and electrical failure analysis (FA) reveal that all major failures occurred because of an abnormally weak G-S disturbance immunity. In addition, the temperature dependency of the G-S disturbance implies that the failure mechanism is related to Co-spike rather than midgap trap-induced junction leakage. Although abnormal defects are not detected through physical FA, by using simple failure modeling and a process split test, we verified the root cause of a new type of erratic failure. The single-bit disturbance failure can be explained as electrons generated in the floating junction area being accelerated in the G-S stress mode, resulting in soft programming by the channel hot electron (CHE) injection mechanism.

Degradation of gate-recessed MOS-HEMTs and conventional HEMTs under DC electrical stress* *Project supported by the Laboratory Open Fund of Beijing Smart-chip Microelectronics Technology Co., Ltd and the National Natural Science Foundation of China (Grant No. 11690042), the Science Challenge Project, China (Grant Nos. TZ2018004 and 12035019), and the National Major Scientific Research Instrument Projects, China (Grant No. 61727804).

The performance degradation of gate-recessed metal–oxide–semiconductor high electron mobility transistor (MOS-HEMT) is compared with that of conventional high electron mobility transistor (HEMT) under direct current (DC) stress, and the degradation mechanism is studied. Under the channel hot electron injection stress, the degradation of gate-recessed MOS-HEMT is more serious than that of conventional HEMT devices due to the combined effect of traps in the barrier layer, and that under the gate dielectric of the device. The threshold voltage of conventional HEMT shows a reduction under the gate electron injection stress, which is caused by the barrier layer traps trapping the injected electrons and releasing them into the channel. However, because of defects under gate dielectrics which can trap the electrons injected from gate and deplete part of the channel, the threshold voltage of gate-recessed MOS-HEMT first increases and then decreases as the conventional HEMT. The saturation phenomenon of threshold voltage degradation under high field stress verifies the existence of threshold voltage reduction effect caused by gate electron injection.

APPLICATIONS OF TCAD SIMULATION SOFTWARE TO THE STUDY OF FLOATING-GATE DEVICE

The floating-gate device has become an established component of all electronic systems, especially Non-volatile memories in recent years. This paper produces a study for this device including the structure and operation (read, program/write and erase). A complete flow which uses ATHENA, ATLAS and DEVEDIT3D tools for 2D and 3D structure simulations including I-V characteristics, Channel Hot Electron Injection, and Fowler-Nordheim Tunnel simulations are performed in TCAD environment.

Research for Hot Carrier Degradation in N-Type Bulk FinFETs

In this paper, the effect of hot carrier injection on an n-bulk fin field-effect transistor (FinFET) is analyzed. The hot carrier injection method is applied to determine the performance change after injection in two ways, channel hot electron (CHE) and drain avalanche hot carrier (DAHC), which have the greatest effect at room temperature. The optimum condition for CHE injection is VG=VD, and the optimal condition for DAHC injection can be indirectly confirmed by measuring the peak value of the substrate current. Deterioration by DAHC injection affects not only hot electrons formed by impact ionization, but also hot holes, which has a greater impact on reliability than CHE. Further, we test the amount of drain voltage that can be withstood, and extracted the lifetime of the device. Under CHE injection conditions, the drain voltage was able to maintain a lifetime of more than 10 years at a maximum of 1.25 V, while DAHC was able to achieve a lifetime exceeding 10 years at a 1.05-V drain voltage, which is 0.2 V lower than that of CHE injection conditions.

Unsupervised Learning by Spike-Timing-Dependent Plasticity in a Mainstream NOR Flash Memory Array—Part I: Cell Operation

This article and its part II demonstrate the possibility to operate a mainstream NOR Flash memory array as an artificial synaptic array learning without external supervision according to the spike-timing-dependent plasticity (STDP) rule. As a first mandatory step to this aim, suitable array working conditions allowing not only selective cell programming but also selective cell erase are here identified, overcoming the block erase operation typical of any Flash memory technology. The proposed array working conditions exploit channel hot-electron injection and hot-hole injection at the drain side to achieve selective, bidirectional, and virtually analog tuning of cell threshold voltage, with no need for changes in the design of a common-ground double-polysilicon NOR array. In part II, the new working scheme will be shown to allow for a straightforward implementation of STDP and unsupervised learning in the array.

Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

Comprehensive study of hole injection in non-overlapped implantation n-type MOSFETs

The promising use of non-overlapped implantation (NOI) n-type MOSFETs as nonvolatile memory (NVM) devices has received considerable interest owing to their simple device structure and compatibility with logic CMOS processing. In NOI n-type MOSFETs, the charge distribution by channel hot electron injection (CHEI) programming markedly differs from that in other charge trapping devices in terms of electron injection distribution. In this study, hot hole injection (HHI) in NOI NVM devices is investigated using Technology Computer Aided Design (TCAD) simulations, measured program/erase speeds, and charge pumping (CP) techniques. Furthermore, HHI efficiency is theoretically deduced and compared with that of silicon–oxide–nitride–oxide–silicon (SONOS) devices. Similar to the results for SONOS device, the lateral fields by VD biases significantly enhance HHI for erasing NOI devices. However, preprogrammed electrons are also dominant in erasing NOI devices. On the basis of the CP results, the hole distribution by HHI in NOI NVM devices strongly correlates with the distribution of preprogrammed electrons.

High Performance of Fin-Shaped Tunnel Field-Effect Transistor SONOS Nonvolatile Memory With All Programming Mechanisms in Single Device

This paper demonstrates a silicon-oxide-nitrideoxide-silicon (SONOS) nonvolatile memory (NVM) with fin-shaped polycrystalline silicon channel tunnel field-effect transistor (TFET). It differs from other memory devices in that its programming mechanisms include Fowler-Nordheim (FN) tunneling, channel hot-electron (CHE) injection, and band-to-band tunneling-induced hot electron (BBHE) in single memory cell. In FN programming, both the ON-state current and the program/erase (P/E) operations are based on quantum tunneling. For FN tunneling, when a V \(_{{{\rm G}}}\) of 17 V is applied for only 1 ms, this device has a large threshold voltage shift ( \(\Delta V_{\mathrm {\mathbf {TH}}}\) ) of 4.7 V. The fin-shaped TFET SONOS (T-SONOS) NVM exhibits superior endurance of 88% after 104 P/E cycles. The memory window remains 65% of its original value after 10 years at a high temperature of 85 °C. On the other hand, the device exhibits better endurance of 74% for CHE programming and BBHE programming after 104 P/E cycles. The memory window retains 81% in CHE programming and 65% in BBHE programming after 10 years. The fin-shaped T-SONOS NVM exhibits high performance that can be achieved in polycrystalline silicon NVM.

Study of charge loss mechanisms for nano-sized localized trapping SONOS memory devices

Data retention loss mechanisms in nano-sized localized trapping polysilicon–oxide–nitride–oxide–silicon (SONOS) memory devices were investigated. To study the influence of charge lateral distribution on data retention, we used three channel hot electron injection (CHEI) programming operations with different substrate biases and same erasing operations to obtain three different charge profiles in the nitride layer after successive program/erase cycling. As a result, the mismatch profile of injected electrons and holes leads to serious degradation of data retention for the negative substrate biased CHEI programming. The experimental results suggest that the residual holes accumulation due to the mismatched profile, evidenced by the charge pumping and sub-threshold slope measurement, could be one of main origins of charge loss for nano-sized cycled SONOS cells. When the mismatch of the injected electrons and holes profiles is very serious after cycling, the accumulated holes detrapping by Frenkel–Poole emission and the lateral transport in the nitride layer may be an important data loss mechanism.

The promising multi-bit/level programming operations for nano-scaled SONOS memory

In order to obtain a reliable multi-bit/level operation for nano-scaled polycrystalline silicon-oxide-nitride-oxide-silicon (SONOS) memory, two different localized charge-injection programming methods, the channel hot electron injection with a positive substrate bias (CHEI-P) and pulse agitated substrate hot electron injection (PASHEI), are operated in 90nm SONOS cells. It is found that the cells programmed by CHEI-P have the better endurance property than by PASHEI. The better endurance is due to the less accumulation of charges in the nitride layer, evidenced by surface potential profiling technique. CHEI-P program further exhibits the superior endurance and retention properties after 104 program/erase cycles in 4-bit/4-level operations. These results illustrate that CHEI-P program is a promising candidate for multi-bit/levels nano-sized SONOS memory.

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

An adequate gate coupling ratio (GCR) and compensation for floating-gate to floating-gate (FG-to-FG) coupling interference must be maintained to enable further scaling of virtual-ground multilevel-cell (MLC) FG flash memory. A high GCR of 0.6 is obtained using a novel bowl-shaped FG structure cell technology without sacrificing cell size. Increasing the GCR is important for reducing FG-to-FG coupling interference and achieving low-voltage operation. A novel array segmented virtual-ground architecture with bit-line isolation between neighboring segments and two-step programming with the channel hot electron injection threshold voltage compensation technique are proposed to reduce the number of neighboring cells that are programmed after programming a given cell, as well as the amount of threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) shift of the neighboring cells. Adoption of this programming approach realizes a reduction in the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift caused by the FG-to-FG coupling interference in the bit-line direction, compared with conventional programming approaches, and the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift is almost completely eliminated in the word-line direction without sacrificing program throughput. The proposed virtual-ground MLC FG cell, which is as small as 3F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit ( F is the minimum feature size) is successfully implemented into a test chip with good reliability.

A Four-Bit-Per-Cell Program Method with Substrate-Bias Assisted Hot Electron Injection for Charge Trap Flash Memory Devices

We propose a four-bit-per-cell program method using a two-step sequence with substrate-bias assisted hot electron (SAHE) injection into the charge trap flash memory devices in order to overcome the limitations of conventional four-bit program methods, which use channel hot electron (CHE) injection. With this proposed method, a localized charge injection near the junction edge with an acceptable read margin was clearly observed, along with a threshold voltage difference of 1 V between the forward and the reverse read. In addition, a multi-level storage was easily obtained using a drain voltage step of 1 V at each level of the three programmed states, along with a fast program time of 1 micros. Finally, by using charge pumping methods, we directly observed the detailed information on the spatial distribution of the local threshold voltage in each level of the four states, for each physical bit, as a function of the program voltage.

Design of DC-DC Converter for Flash Memory IPs

A DC-DC converter for flash memory IPs performing erasing by the FN (Fowler-Nordheim) tunneling and programming by the CHEI (channel hot electron injection) is designed in this paper. For the DC-DC converter for flash memory IPs using a dual voltage of VDD (=1.5V±0.15V)/VRD (=3.1V±0.1V), a scheme of using VRD (Read Voltage) instead of VDD is proposed to reduce the pumping stages and pumping capacitances of its charge pump circuit. VRD (=3.1V±0.1V) is a regulated voltage by a voltage regulator with an external voltage of 5V, which is used as the WL activation voltage in the read mode and an input voltage of the charge pump. The designed DC-DC converter outputs positive voltages of VP6V (=6V), VP8V (=8V) and VP9V(=9V); and a negative voltage of VM8V (=-8V) in the write mode.

An improved multilevel cell programming technique for 4-bits/cell localized trapping SONOS memory devices

As the cell size scales down to 90nm node, the mismatch of spatial charge distribution dramatically aggravates the reliability degradation of localized trapping polysilicon–oxide–nitride–oxide–silicon (SONOS) memory, especially in multilevel cell and multi-bits/cell applications. The secondary electron injection (SEI) is thought to be the root cause of mismatch between injected electrons and holes. A channel hot electron injection (CHEI) programming technique with a positive substrate bias was proposed to effectively suppress SEI effect. In this work, a similar programming method is used in 90nm localized trapping SONOS devices for multilevel cell and multi-bits/cell storage. In contrast to the reported positive substrate biased CHEI programming, we apply a source bias of 1V instead of 0V to prevent the forward-biased source/substrate junction so that the programming power consumption is greatly reduced. It is experimentally found that a sharp electron profile near the junction edge is obtained. A better matched profile of the injected electrons and holes substantially improves the cycling endurance and data retention of 4-bits/cell memory at the four-level states.

Fabrication and Characterization of NOR-Type Tri-Gate Flash Memory with Improved Inter-Poly Dielectric Layer by Rapid Thermal Oxidation

Floating-gate (FG)-type tri-gate flash memories with an improved inter-poly dielectric (IPD) layer have been successfully fabricated by introducing a newly developed rapid thermal oxidation (RTO) process, and their NOR-mode operation including threshold voltage (Vt) variations before and after one program/erase (P/E) cycle have been systematically investigated. It was experimentally confirmed that the gate breakdown voltage (BVg) is greatly increased from 12 to 19 V by introducing the RTO process thanks to the high quality and thin thermal silicon dioxide (SiO2) formation on the FG surface and etched edge regions, which effectively blocks the leakage pass of the IPD layer. A source–drain (SD) breakdown voltage (BVDS) as high as 4.5 V was obtained even when the gate length (Lg) was as small as 117 nm. It was also experimentally confirmed that the memory window increases with increasing gate voltage (Vg) in NOR-mode programming thanks to the increased efficiency of channel hot electron (CHE) injection. The developed tri-gate flash memory with improved IPD layer is useful for the further scaling of NOR-type flash memory.

An Efficient Nonlocal Hot Electron Model Accounting for Electron–Electron Scattering

This paper presents a nonlocal model for channel hot electron injection in MOSFETs and nonvolatile memories, which includes a full-band description of optical phonon scattering rates and carrier group velocity. By virtue of its efficient formalism, this model can also include carrier-carrier scattering, which has a marked impact on gate current at low gate voltages. The model is compared against full-band Monte Carlo simulations of typical nor flash devices in terms of distribution functions, bulk current, gate current, and gate current density along the channel. A very good agreement is obtained for various drain and gate voltages and channel lengths.

Investigation of STI edge effect on programming disturb in localized charge trapping SONOS flash memory cells

Abstracts The impact of shallow trench isolation (STI) on non-volatile memories has become much more serious for sub-90-nm CMOS technologies. This paper uses the localized charge trapping polysilicon-oxide-nitride-oxide-silicon (SONOS) flash memory cells to investigate STI edge effect on programming disturb when the channel hot electron injection programming method is applied. The different programming disturbs between the central cells far from STI and the edge cells close to STI are experimentally presented on the array level. At the programmed state, the edge cells suffer larger decrease of threshold voltage compared to the central cells under the same drain disturb. However, both edge and central cells at the erased state have not any significant variations of threshold voltage distribution under the same disturb conditions. In addition, both edge and central cells demonstrate almost the same behaviors under gate disturb. Two-dimension process simulation results show that the edge cells suffer a higher compressive stress caused from STI corner than the central cells. The higher compressive stress increases hole mobility, which is mainly responsible for the relatively serious drain disturb in the programmed edge cells.