Channel Flash Research Articles

3-D AND-Type Flash Memory Architecture With High-κ Gate Dielectric for High-Density Synaptic Devices

Advanced 3-D synaptic devices with a stackable AND-type rounded dual channel (RDC) flash memory structure are proposed for neuromorphic networks. AND synaptic arrays composed of RDC flash devices enable program/erase (PGM/ERS) using Fowler–Nordheim (FN) tunneling, high-speed operation because of parallel read operations, and high density with multilayer stacking. Key fabrication steps are explained and the successful operation of the device in 3-D stacked structure is verified by measurement results. In addition, current summation and selective PGM/ERS behavior in synaptic arrays, which are essential in neuromorphic networks, are demonstrated. A hardware-based convolutional neural network (CNN) is designed considering the operating characteristics of the RDC flash memory. The accuracy evaluation and analysis for the CIFAR-10 image classification are performed. In addition, we propose a method of constructing a hardware-based CNN with the high-density synaptic array by stacking layers.

A Novel Program Scheme for Program Disturbance Optimization in 3-D NAND Flash Memory

A new program scheme using an “erase-like” waveform for precharge operation is proposed for program disturbance optimization in 3-D vertical channel flash memories. With the proposed scheme, the effect of precharge operation, which is followed by program operation, on the initial unselected channel is enhanced by charging additional holes from p-type well. Consequently, boosting efficiency and boosting potential of unselected string are promoted, leading to a significant suppressed program disturbance, and the ${V}_{\textsf {pass}}$ window can be enlarged notably as well. Meanwhile, the timing requirement of the proposed scheme is evaluated. The advantage of the erase assisted precharge scheme has been demonstrated by TCAD simulation and measurement in mini-array test-key device.

A Novel Read Scheme for Read Disturbance Suppression in 3D NAND Flash Memory

A new read scheme is proposed to suppress read disturbance in unselected strings of three-dimensional (3D) vertical channel flash memories. This new scheme decreases the channel potential difference between select word-line (WL) and adjacent WL by more than 20% and the read disturb due to hot carrier injection in adjacent WL of selected WL is suppressed effectively by about 95%. Meanwhile, boosted channel potential during read operation has been preserved to improve soft programming read disturbance by more than 85% in non-adjacent unselected memory cells, owing to the reduced electric field across tunnel oxide. Compared with the conventional scheme, the proposed scheme leads to a significant improvement in read disturbance characteristics with a shorter read period as well as a simplified waveform of read operation.

(Invited) Floating Gate Type SOI-FinFET Flash Memories with Different Channel Shapes and Interpoly Dielectric Materials

The floating gate (FG)-type silicon-on-insulator (SOI)-FinFET flash memories with triangular-fin (TF) and rectangular-fin (RF) channels and with different interpoly dielectric (IPD) materials have been successfully fabricated using (100)- and (110)-oriented SOI wafers and orientation dependent wet etching. The electrical characteristics of the fabricated FG-type SOI-FinFET flash memories including threshold voltage (Vt) variability, program/erase (P/E) speed, memory window, endurance, and data retention at room temperature and 85 oC have been comparatively investigated. It was experimentally found that the TF channel flash memory with an Al2O3-nitride-oxide (ANO) IPD layer shows a higher P/E speed, a larger memory window, and a lower-voltage operation as compared to the RF channel flash memories with the same ANO IPD layer. Such a high performance of the TF-ANO flash memory is due to the high-k effect of the Al2O3 layer and the electric field enhancement at the sharp foot edges of the TF.

Channel shape and interpoly dielectric material effects on electrical characteristics of floating-gate-type three-dimensional fin channel flash memories

Floating-gate (FG)-type three-dimensional (3D) fin channel flash memories with triangular fin (TF) and rectangular fin (RF) channels and different interpoly dielectric (IPD) materials have been successfully fabricated using (100)- and (110)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. The electrical characteristics of the fabricated FG-type 3D fin channel flash memories including threshold voltage (Vt) variability, program/erase (P/E) speed, memory window, endurance, and data retention at room temperature and 85 °C have been comparatively investigated. A higher P/E speed, a larger memory window, and a lower-voltage operation are experimentally obtained in the TF channel flash memories with an Al2O3–nitride–oxide (ANO) IPD layer (TF-ANO) than in the RF channel ones with the same ANO IPD layer (RF-ANO) and the TF channel ones with an oxide–nitride–oxide (ONO) IPD layer (TF-ONO). The larger memory window and lower-voltage operation of TF-ANO flash memories are due to the high-k effect of the Al2O3 layer and the electric field enhancement at the sharp foot edges of the TF channels. It was also found that data retention for all fabricated FG-type 3D fin channel flash memories shows a weak dependence on temperature.

Characteristics of gate-all-around polycrystalline silicon channel SONOS flash memory

In this study, the gate-all-around (GAA) poly-Si channel flash memories with a nitride charge trap layer (Si 3 N 4 ) have been successfully fabricated. Electrical characteristics of fabricated devices including the threshold voltage shift with program/erase operation have been investigated. Gate structures were formed differently according to each defined channel width. Results show that devices with the gate-all-around structure have superior program efficiency. To investigate the effect of gate structure on the program efficiency, TCAD simulation was carried out. Another issue of the fabricated devices is poor erase operation due to the quality of the blocking oxide. This issue has been studied through the capacitor composed of the same stack structure, and the way to improve the erase operation has been proposed.

Improved programming and erasing speeds of poly-Si flash memory device by HfO2/Si3N4 bandgap-engineered trapping layer

• HfO 2 /Si 3 N 4 bandgap-engineered trapping layer is applied to nanowire flash device for the first time. • P/E speeds can be significantly improved by bandgap-engineered trapping layer. • The improvement is more obvious on nanowire channel flash device. • Good retention and endurance characteristics are also demonstrated. Effects of HfO 2 /Si 3 N 4 bandgap-engineered trapping layer (BETL) on poly-Si flash memory device are studied for the first time. Planar and nanowire (NW) channel flash memory devices are successfully fabricated to study the effects of BETL. The programming and erasing speeds can be improved by BETL on both planar and NW channel devices, and the improvement is more obvious on NW channel devices with even a lower operation voltage. The device with BETL and NW channel demonstrates the best programming and erasing speeds due to the electric-field enhancement effect and the band-engineering in charge-trapping layer. It also shows good retention and endurance properties, which makes it promising for 3-D memory integration.

Design of High-Speed and Low-Power Two-Channel Pipeline ADC

This paper describes a low-power 1.2 V 8-bit 1Gs/s two-channel pipeline ADC. The novelty of the designed ADC lies in: ameliorating the two-channel pipeline structure that consists of 1.5-bit multiplying DAC (MDAC). In order to reduce the power consumption and improve the sampling speed, the dual-channel pipeline Time Division Multiplexing operation amplifier and double or single channel flash ADC are used; in the front-end Sample-and-Hold circuits, switch-linearization control circuits(SLC) driven by a single clock signal is applied to solve the problem of time-skew and time mismatch between two channels. The pipeline ADC is designed with 90 nm CMOS process. From the simulation results of the designed ADC, we can draw that the SFDR is 42.3 dB; the SNR is 32.7 dB under the usual temperature. The ADC achieves 21 mW power-dissipation, 8 resolution and 1.01 GS/s sampling speed. So the design meets high speed, high precision and low power dissipation at the same time.

Statistics and characteristics of cloud‐to‐ground lightning with multiple ground contacts

During the summer of 1997, 386 cloud‐to‐ground (CG) lightning flashes were recorded on videotape near Tucson, Arizona. Within this sample, 136 flashes (35%) struck the ground in two or more places that were separated by tens of meters or more. Within this subset of 136, which we term “multiple channel flashes” (MCFs), 88 exhibited two or more separate and distinct channels between the cloud base and the ground, a type that we term a “new channel flash” (NCF); 37 forked or produced channels that struck the ground in two or more places and shared a common channel at higher altitudes, a type that we term an “altered channel flash” (ACF); and 11 exhibited both types of behavior. The ratio of NCFs to ACFs in Arizona was 99/48 or 2.1, a value that is consistent with measurements in Florida after allowing for differences in the cloud base heights. Altogether, the 386 CG flashes produced 558 different strike points; therefore, the average number of strike points per CG flash was 1.45. 67% of the new strike points were produced by the second stroke in the flash, and 72% of the changes in channel geometry occurred after there had been just one stroke in the previous channel. Ten of the 48 ACFs (21%) developed along a visible branch of the previous channel, and seven of the 136 MCFs (5%) contained strokes that reilluminated the first channel after a second channel had formed. The presence of a long, continuing luminosity during the initial three or more consecutive video frames appeared to lower the probability of forming either a new or altered channel on the second stroke (from 47% to 33%), but the statistics are limited, and our ability to identify individual strokes is biased by poor time resolution.

New buried channel flash memory cell with symmetrical source/drain structure

New buried channel flash memory cell with symmetrical source/drain structure

Formulas for calculating the approach to equilibrium in open channel flash evaporators for saline water

The evaporator used in multistage flash desalination plants, and considered for open cycle ocean-thermal energy conversion (OTEC) plants is the open-channel type, in which an essentially-horizontal stream of seawater is passed through an open channel in which it is exposed to a pressure lower than the saturation pressure which corresponds to its temperature. This paper reviews the equations used at present to determine the nonequilibrium allowance Δ′ which indicates how far from equilibrium the seawater stream is as it leaves the evaporator. Flash evaporation in open channels is used in most of the water desalination plants, and the existing equations for Δ′ have been developed for that application. The equations are typically empirical correlations, each developed for one type of geometry and range of parameters. The equations are compared graphically, plotted side-by-side to express Δ′ as a function of the major parameters: stage saturation temperature, stage flash-down, flashing seawater flow rate, stage length, and flashing seawater depth. It was found for water desalination applications that there exists a large spread between the non-equilibrium fraction values calculated by the different equations, of about one order of magnitude. The situation is even worse for OTEC conditions. Consequently, it was concluded that no general method exists for the adequately accurate prediction of Δ′, i.e. of the approach to equilibrium of flashing free stream channel flows.