Channel Engineering Research Articles

Solution Processed Organic Thin-Film Transistors With Hybrid Low/High Voltage Operation

Solution processed bottom-gate bottom-contact organic thin-film transistors (OTFTs) being able to sustain hybrid low/high voltage operation were realized with the maximum processing temperature not exceeding 100 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C. In the devices, a channel engineering approach is used to achieve low voltage operation, by inducing phase separation with the blend of 6, 13-bis(triisopropylsilylethynyl)-pentacene and polystyrene to form an ultra-thin high crystalline channel. Since the approach doesn't rely on enlarging the gate dielectric capacitance, the low voltage OTFT with a relatively thick dielectric layer was shown to be able to sustain high voltage operation. Moreover, the ultra-small dielectric capacitance can help to reduce the parasitic capacitance in the data and scan lines of the display panel. The device technology is shown to be promising for developing flexible/rollable display systems on plastic substrates, where a relatively high voltage is required for the pixel driving circuits, and a low voltage is preferred for the logic circuits in the peripheral drivers.

EXPERIMENTAL STUDY ON DEEPWATER CHANNEL REGULATION SCHEME OF TONGZHOU SHOAL AND BAIMAO SHOAL

The Deepwater Channel Phase III Regulation Project of Yangtze Estuary was completed and approved in March 2010, and deepwater channel has been extended to Dangxikou of Taicang City at the end of 2010. According to the national plan, in order to give full play to the benefits of the Yangtze river golden channel, the 12.5m deepwater channel will be extended to reach Nanjing Harbor, thus about 400km long 12.5m deepwater channel will be constructed. Therefore, deepwater channel of Nanjing downstream project is carried out by Ministry of Transportation and Communication and Jiangsu Province Government. The project is another major water transportation engineering following the Yangtze estuary deepwater channel regulation project. The project will be implemented in two phases, in which phase I is located in Taicang～Nantong reach of Yangtze River, immediately following the completed Yangtze Estuary 12.5m deepwater channel. There are two major navigation-obstructing channels in this reach —— Tongzhou Shoal channel and Baimao Shoal channel. Based on preliminary works of riverbed evolution analysis, mathematical model calculation and other researches, depended on existing large-scale and wide-range Yangtze River estuary model, fixed and movable bed physical model tests were used to study the comparable feasibility scheme and optimization scheme. Through analysis, four fixed bed model and three movable bed model representative hydrodynamic conditions were considered, channel regulation effects, beach protection effects, and influences on river regime, flood control and nearby regions after implementing the two engineering schemes were all comparatively analyzed from water level, velocity, flow direction, braided channel diversion ratio, riverbed erosion and deposition and other aspects. Studies suggest that: after implementing the two engineering schemes, the planned 12.5m channel is continuous, the 500m×12.5m requirement is satisfied with slight dredging; compared with the feasibility scheme, beach protection effects of optimization scheme for Tongzhou Shoal is roughly equal with the feasibility scheme, while for Baimao Shoal, the optimization scheme is better; in optimization scheme, the head of tooth dikes are extended forward, the velocity of shallow areas increased slightly, channel depth improvement effect is better; Langshan Shoal tail submerged dike of optimization scheme can increases the stability of Langshan Shoal tail, and local scouring is decreased. In general, optimization scheme can be the recommend scheme, regulation effects of it are better than feasibility scheme. The relevant results have been used in channel engineering design and decision making.

Keynote; Material Challenges and Opportunities in Ge/III-V Channel MOSFETs

CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of promising devices for high performance and low power logic LSIs in the future. There can be several CMOS structures using III-V/Ge channels. One of the ultimate CMOS can be the co-integration of a III-V nMOSFET and a Ge pMOSFET. While Ge or III-V CMOS is also plausible in terms of the simplicity of the material integration, the key issues are the realization of high performance Ge nMOSFETs or III-V pMOSFETs. Also, even in Ge pMOSFETs and III-V nMOSFETs, the CMOS technologies have not been established yet. Thus, viable CMOS structures using III-V and/or Ge channels are still strongly dependent on coming progress in the device/process/integration technologies.In addition, one of the most important issues for applying to the future technology nodes is suppression of short channel effects, which can be realized by ultrathin body (UTB) channels. Particularly, we would prefer planar UTB/UTBOX-based structures, which can realize further improvement of short channel effects by combination with multi-gate structures such as FinFET and Tri-gate/nanowire MOSFETs. This scheme allows us to provide static and/or dynamic Vth control through UTBOX by Si substrate doping and back bias under simple structures and fabrication processes. Here, the difficult challenges for realizing high performance logic devices include the III-V/Ge ultrathin body channel formation, the low resistivity S/D formation, the mobility enhancement in such ultrathin body channels and superior MOS gate stacks. Our approach for the channel formation is the wafer bonding for III-V materials and the Ge condensation technique for Ge/SiGe channels. Also, metal S/D technologies are regarded as promising for reducing parasitic S/D resistance. In order to maintain high channel mobility, we employ optimized channel design of quantum wells (QW) with MOS interface buffers for III-V channels, and surface orientation and strain engineering for Ge channels. The GeOx-based gate stacks are important for obtaining high mobility Ge MOSFETs with ultrathin EOT. We have proposed and demonstrated UTB InGaAs-based channel formation for III-V nMOSFETs by using direct wafer bonding. Ultrathin body (3.2 nm InGaAs)/UTBOX (Al2O3(4.4 nm)/SiO2(3.3 nm)) substrates are realized with high material quality. As channel engineering to boost the mobility in UTB InGaAs-based channels, we have introduced two boosters, higher In content InAs channels and MOS interface buffers composed of lower-In-content buffers. Based on these technologies, we have realized sub-20-nm-channel-length Tri-gate InGaAs/InAs/InGaAs-OI QW MOSFETs with good electrostatic. Here, wide-range Vth tunability in Tri-gate InAs-OI MOSFETs through VB control has been demonstrated. As for III-V pMOSFETs, we have also demonstrated UTB GaSb-OI pMOSFETs on Si by using wafer bonding. Based on these technologies, a novel III-V CMOS structure composed of GaSb/InAs hetero-structures is proposed.One of the most critical issues in Ge MOSFETs is the realization of gates stacks with superior MOS interfaces. In order to realize low Dit, high mobility and thin EOT at the same time, we have proposed a interfacial layer formation process employing ECR oxygen plasma to form GeOx ILs after thin Al2O3 or HfO2/Al2O3 ALD. This ultrathin GeOx IL is found to effectively reduce Dit in both valence and conduction band sides. N- and p-MOSFETs with the HfO2/Al2O3/GeOx/Ge gate stacks exhibit the excellent electrical characteristics under EOT of 0.76 nm. In spite of this ultrathin EOT, high electron and hole mobility is obtained in comparison with the thick GeO2/Ge mobility and the Si mobility, particularly in high Ns region. These results strongly demonstrate that HfO2/Al2O3/GeOx/Ge gate stacks can realize high performance Ge n- and pMOSFETs with minimal mobility expense under aggressive scaling of EOT.

Channel engineering of ZnO-based thin film transistors using Al2O3 interlayer grown by atomic layer deposition

In this study, an Al2O3 interlayer is grown between the ZnO channel layer and the gate dielectric by atomic layer deposition to improve the electrical characteristics of ZnO-based thin film transistors (TFTs). From the current–voltage measurements, superior electrical performance characteristics are confirmed, such as superior subthreshold swing and on-/off-current ratio. On the basis of the results of X-ray diffraction (XRD) analysis, the enhanced properties can be explained by large grains in the ZnO channel layer that is deposited on Al2O3. However, when ZnO grains are aligned in the (002) direction, the stability characteristics under positive bias stress become inferior, which is considered to be caused by considerable oxygen adsorption at the nonpassivated channel surface owing to Zn polar extension.

Dependence of interface charge trapping on channel engineering in pentacene field effect transistors.

We investigate the dependence of charge carrier mobility by trap states at various interface regions through channel engineering. Prior to evaluation of interface trap density, the electrical performance in pentaene field effect transistors (FET) with high-k gate oxide are also investigated depending on four channel engineering. As a channel engineering, gas treatment, coatings of thin polymer layer, and chemical surface modification using small molecules were carried out. After channel engineering, the performance of device as well as interface trap density calculated by conductance method are remarkably improved. It is found that the reduced interface trap density is closely related to decreasing the sub-threshold swing and improving the mobility. Particularly, we also found that performance of device such as mobility, subthreshold swing, and interface trap density after gas same is comparable to those of OTS.

Dual-&lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;$V_{\rm th}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; Low-Voltage Solution Processed Organic Thin-Film Transistors With a Thick Polymer Dielectric Layer

Threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) control using different metal gates (aluminum and gold) was applied to realize dual-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> low-voltage solution processed organic thin film transistors (OTFTs). In the devices, the low-operation voltage was realized based on a channel engineering approach instead of using large gate dielectric capacitance, therefore, a relatively thick and low-dielectric constant polymer dielectric layer can be used. The devices present a mobility about 1.0 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /(V·s), ON/OFF ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> and small subthreshold swing of 100 mV/decade with the maximum processing temperature not exceeding 100 °C. It was found that, even with a 400-nm thick polymer dielectric layer, since possible charge trapping effects was effectively suppressed by the crosslinking processes, well controlled V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> was achieved. Both unipolar single-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> and dual-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> inverters were fabricated, clearly showing the influence of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> on the circuit operation and improved performance with the dual-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> OTFT technology.

Attribution of climate change, vegetation restoration, and engineering measures to the reduction of suspended sediment in the Kejie catchment, southwest China

Abstract. Suspended sediment transport in rivers is controlled by terrain, climate, and human activities. These variables affect hillslope and riverbank erosion at the source, transport velocities and sedimentation opportunities in the river channel, and trapping in reservoirs. The relative importance of those factors varies by context, but the specific attribution to sediment transfer is important for policymaking, and has wide implications on watershed management. In our research, we analyzed data from the Kejie watershed in the upper Salween River (Yunnan Province, China), where a combination of land cover change (reforestation, as well as soil and water conservation measures) and river channel engineering (sand mining and check dam construction) interact with a changing climate. Records (1971–2010) of river flow and suspended sediment loads were combined with five land-use maps from 1974, 1991, 2001, 2006 and 2009. Average annual sediment yield decreased from 13.7 t ha−1 yr−1 to 8.3 t ha−1 yr−1 between the period 1971–1985 and the period 1986–2010. A distributed hydrological model (Soil and Water Assessment Tools, SWAT) was set up to simulate the sediment sourcing and transport process. By recombining land-use and climate data for the two periods in model scenarios, the contribution of these two factors could be assessed with engineering effects derived from residual measured minus modeled transport. Overall, we found that 47.8% of the decrease was due to land-use and land cover change, 19.8% to climate change, resulting in a milder rainfall regime, 26.1% to watershed engineering measures, and the remaining 6.3% was due to the simulation percent bias. Moreover, mean annual suspended sediment yield decreased drastically with the increase of forest cover, making diverse forest cover one of the most effective ecosystems to control erosion. For consideration of stakeholders and policymakers, we also discuss at length the modeling uncertainty and implications for future soil and water conservation initiatives in China.

Performance Analysis of Unambiguous Tracking Algorithms for BOC Modulated GNSS Signals

BOC modulation is a major modulation of the new generation GNSS systems. Compared with the existing BPSK modulation, BOC modulation has a better pseudo-code accuracy and better resistance to multipath and interference performance. However, BOC modulation also brings tracking ambiguity problem caused by the vice correlation peak. A series of algorithms have been proposed to eliminate ambiguity, such as Single Side lobe, CCRW ASPeCT, Bump-Jump, DET, and so on. The principle of these algorithms, achievement of difficulty and the performance is not the same. In this paper, a low-level BOC (1,1) signal and a higher order BOC (15,2.5) signal is taken into consideration, performance of those above mainstream algorithms to eliminate ambiguity is simulated and the resource depletion is analyzed. Then, a compatible algorithm is proposed to adapt different BOC signals. The research has a certain reference value for the receiver’s BOC tracking channel design and engineering implementation.

Back Cover: Tin – an unlikely ally for silicon field effect transistors? (Phys. Status Solidi RRL 4/2014)

A low-cost simple thin film deposition of tin (Sn), followed by thermal annealing based alloying of it into the silicon channel, leads to an enhancement of the performance of silicon-based CMOS devices. Modelling based on density functional theory (DFT) shows that Sn incorporation may lower the band gap of the silicon channel, while the experimental multi-gate field effect transistor devices show performance enhancement. Additionally, the device performance analysis indicates its promising usage in low standby power applications for ultra-mobile computation. The study by Aftab M. Hussain et al. (pp. 332–335) opens up further exploration opportunity for group IV(a) (in the periodic table) based materials for channel engineering in semiconductor device technology.

An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering

An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model.

A computational study of gate and channel engineering for GNRFETs performance enhancement

In this article, the effects of single-material-gate (SMG), halo doping (HALO), triple-material-gate (TMG) and triple-material halo doping (TMG-H) structures on electrical characteristics have been investigated for double gate graphene nanoribbon field-effect transistors (GNRFETs) using a full quantum transport simulation. The simulations are based on non-equilibrium Green’s functions (NEGF) solved self-consistently using 3D-Poisson’s equations. The results reveal that a larger difference between the work functions of gate metals of TMG structure will result in increasing the on–off current ratio in GNRFETs. HALO structure reduces the leakage current and alleviates the short channel effects (SCEs) like drain-induced barrier-lowering. Because of the perceivable steps in surface potential profile, which leads to additional lateral electric field peak along the channel, TMG and TMG-H structures have a larger average lateral electric field along the channel, which significantly promotes the transport efficiency and thus improves the subthreshold characteristics of devices.

A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

Some Device Design Considerations to Enhance the Performance of DG-MOSFETs

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current (<TEX>$I_{off}$</TEX>), on current (<TEX>$I_{on}$</TEX>), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

Transport study of gate and channel engineering on the surrounding-gate CNTFETs based on NEGF quantum theory

In this paper, we comprehensively study the effects of gate and channel engineering on the performances of surrounding-gate CNTFETs using a quantum kinetic model, which is based on two-dimensional non-equilibrium Green functions (NEGF) solved self-consistently with Poisson's equations. The iterative approach between Poisson equation and NEGF has been discussed. For the first time, the influences of double-material-gate and linear doping structures on the CNTFETs have been investigated. The calculated results show that double-material-gate CNTFETs with conventional doping (DMG-CNTFETs) can effectively suppress the drain-induced barrier lowering (DIBL), short-channel effects (SCEs), and achieve better sub-threshold property as compared with single-material-gate CNTFETs with conventional doping (SMG-CNTFETs). Compared with conventional doping, linear doping presents lower leakage current, higher I on /I off ratio, and lower sub-threshold swing, which means a better ability of gate controlling. In addition, we present a detailed discussion of the performances of scaling down, and conclude that DMG structure can meet the ITRS'10 requirements better than SMG, especially that the I on /I off ratio is two orders of magnitude higher than that of ITRS'10 requirements.

(Invited) Performance Enhancement Technologies in III-V/Ge MOSFETs

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/ integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for enhancing the MOSFET performance with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeOx/Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low Dit and high mobility. By using these HfO2/Al2O3/GeOx/Ge gate stacks, Ge n- and p-MOSFETs with EOT of 0. 76 nm have been demonstrated with high electron (690 cm2/Vs) and hole (550 cm2/Vs) mobility. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm By utilizing this channel engineering, 55 nm-Lch quantum well channel InAs-OI n-MOSFETs have been demonstrated with superior short channel effect immunity and fairly high on current.

Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications

In this paper, we propose a laterally graded-channel pseudo-junctionless (GPJL) MOSFET for analog/RF applications. We examine the dynamical performance of GPJL MOSFET and compare it with the common junctionless (JL) MOSFET architecture using a 2-D full-band electron Monte Carlo simulator (MC) with quantum correction. Our results indicate that the GPJL MOSFET outperforms the conventional JL MOSFET, yielding higher values of drain current (I ds), transconductance (g m), and cutoff frequency (f t). Further, the emerging electric field and velocity distributions, as a consequence of the channel engineering introduced by the GPJL MOSFET, result in lower output conductance (g ds) and higher early voltage (V ea). The preeminence of the GPJL transistor over the JL transistor is further illustrated by showing improvements on the intrinsic voltage gain (A vo) in the subthreshold regime, to as high as 61 %. These results indicate that our proposed GPJL MOSFET yields improvement in the analog/RF performance metrics as compared to JL MOSFETs.

Ion-Channels: Goals for Function-Oriented Synthesis

Ion channels provide a conductance pathway for the passive transport of ions across membranes. These functional molecules perform key tasks in biological systems such as neuronal signaling, muscular control, and sensing. Recently, function-oriented synthesis researchers began to focus on ion channels with the goal of modifying the function of existing ion channels (ion selectivity, gating) or creating new channels with novel functions. Both approaches, ion channel engineering and de novo design, have involved synthetic chemists, biochemists, structural biologists, and neurochemists. Researchers characterize the function of ion channels by measuring their conductance in samples of biological membranes (patch clamp) or artificial membranes (planar lipid bilayers). At the single molecule level, these measurements require special attention to the purity of the sample, a challenge that synthetic chemists should be aware of. Ideally, researchers study the function of channels while also acquiring structural data (X-ray, NMR) to understand and predict how synthetic modifications alter channel function. Long-term oriented researchers would like to apply synthetic ion channels to single molecule sensing and to implantat these synthetic systems in living organisms as tools or for the treatment of channelopathies. In this Account, we discuss our own work on synthetic ion channels and explain the shift of our research focus from a de novo design of oligo-THFs and oligo-THF-amino acids to ion channel engineering. We introduce details about two biological lead structures for ion channel engineering: the gramicidin β(6,3) helix as an example of a channel with a narrow ion conductance pathway and the outer membrane porins (OmpF, OmpG) with their open β-barrel structure. The increase and the reversal of ion selectivity of these systems and the hydrophobic match/mismatch of the channel with the phospholipid bilayer are of particular interest. For engineering ion channels, we need to supplement the single-point attachment of a synthetic modulator with the synthesis of a more challenging two-point attachment. The successful function-oriented synthesis of ion channels will require interdisciplinary efforts that include new electrophysiology techniques, efficient synthesis (peptide/protein/organic), and good structural analysis.

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs

In this work a comparison between the performance of current mirrors implemented with uniformly doped and graded-channel (GC) transistors operating down to low temperature (150K) is presented. This analysis has been carried out through experimental measurements of Common-source, Cascode and Wilson current mirrors architectures. The advantages of the use of graded-channel transistors for implementation of current mirrors in comparison to standard ones is discussed, focusing on the increase of output swing and output resistance. In all architectures some performance degradation has been observed with the temperature reduction, although current mirrors with GC transistors still present better performance than those implemented with standard SOI transistors. Two-dimensional numerical simulations were performed in order to further investigate the behavior of graded-channel current mirrors, looking at the bias condition of each transistor in the current mirror architectures. The obtained results indicate that good performance, compared to that of GC current mirrors, may be obtained by combining both standard and graded-channel transistors, rather than using the same channel engineering for all devices in the circuit.

(Invited) Manufacturing of Ultra Thin SOI

Devices using fully depleted undoped channels are among the most promising candidates for the next device generations due to their better immunity to short channel effects (SCE) (1) and to random dopant fluctuation. Channel engineering and control are then critical as silicon thickness fluctuation is a statistical source of VT variability and strained channels provide 47% increase in the drive current for NFETs (2) without any degradation for PFETs (3). SOI substrates from Soitec provide a complete set of manufacturing solutions either for planar or three-dimensional (FinFET) devices as they pre-integrate critical characteristics of the transistors within the wafer structure itself. Substrate robustness and readiness have been demonstrated. For planar devices the SOI thickness uniformity is controlled at +/-5A (6sigma value, all sites, all wafers) in high volume manufacturing mode. For three-dimensional devices, substrate requirements are extremely close to partially depleted ones which are in high volume manufacturing for more than 7 years.

Investigation of the Electrical and Thermal Performance of SOI MOSFETs with Modified Channel Engineering

In this paper, we present a novel type of channel doping engineering, using a graded doping distribution, that improves the electrical and thermal performance of silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs), according to simulations that we have performed. The results obtained include a reduction in the self-heating effect, a reduction in leakage currents due to the suppression of short-channel effects (SCEs), and a reduction in hot-carrier degradation. We term the proposed structure a modified-channel-doping SOI (MCD-SOI) MOSFET. The main reason for the reduction in the self-heating effect is the use of a lower doping density near the drain region in comparison with conventional SOI MOSFETs with a uniform doping distribution. The most significant reason for the leakage current reduction in the MCD-SOI structure is the high potential barrier near the source region in the weak inversion state. The SCE factors, including the drain-induced barrier lowering, subthreshold swing, and threshold voltage roll-off, are improved. A highly reliable structure is achieved owing to the lower doping density near the drain region, which reduces the peak electric field and the electron temperature.