Channel Doping Concentration Research Articles

Split-Gate Induced High-Field for Impact Ionization Triggered Bipolar Action and Sub-kT/q Switching in Junctionless FET

In this article, an energy-efficient, ultra-steep subthreshold slope device based on the split-gate junctionless field-effect transistor (JLFET) has been proposed and investigated. Through split-gate, two regions, namely, channel-1 and channel-2, separated by a gap (<inline-formula><tex-math notation="LaTeX">$L_{gap}$</tex-math></inline-formula>) are created. A high electric field is thus induced at the interface of these two regions, which initiates impact ionization (II) at sub-bandgap drain voltage. The II-generated holes/electrons accumulate in channel-2 of N-JLFET/P-JLFET and set up a floating body that reduces the potential barrier between channel-1 and source of the device resulting in ultra-steep switching. Using a well-calibrated TCAD tool, we analyzed the operation of both N- and P-JLFET. A subthreshold swing (SS) of <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 50&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>V/decade over nearly three decades of drain current is possible while maintaining a low OFF current of <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> <inline-formula><tex-math notation="LaTeX">$4.9\times 10^{-12}$</tex-math></inline-formula> A/<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m at a drain voltage of 0.4&#x00A0;V for silicon N-JLFET, which is better than any of the results reported so far for the junctionless devices. We have also investigated the impact of various device design parameters such as lengths of channel-1, channel-2, channel doping concentration, <inline-formula><tex-math notation="LaTeX">$L_{gap}$</tex-math></inline-formula>, gate oxide thickness and its permittivity, channel thickness, and dual-metal work function on the device performance.

(Invited) Study on Impact of MOS Interface Passivation Processes on Band Alignment and Flat-Band Voltage of 4H-SiC Gate Stacks

A sufficiently large threshold voltage (Vth) is generally demanded for high-voltage power MOSFETs with 4H-SiC, however, the increase in channel doping concentration to tune Vth inevitably induces a significant reduction of carrier mobility in the inversion channel, due to Coulomb scattering at SiO2/4H-SiC interface [1]. Another serious problem is that negative Vth shifts are often observed by employing SiC surface nitridation process, usually done by a post-oxidation annealing (POA) in NO ambient at elevated temperature. Such processes introduce nitrogen atoms selectively to the surface of SiC by substituting the topmost carbon atoms [2]. Currently such nitrogen passivation process is inevitable to fabricate 4H-SiC MOS gate stacks with sufficiently low interface state density and good device reliability. Therefore the development of technique to design Vth of 4H-SiC MOSFETs is strongly demanded based on the understanding of the factors to cause Vth shift.First we systematically studied the flat-band voltage (Vfb) of SiO2/4H-SiC (0001) n-type MOS capacitors with various oxide thickness, fabricated by conventional dry oxidation followed by NO-POA. From the oxide thickness dependence of Vfb we could deduce the expected Vfb value when the effects of fixed charges are removed. As a result we found an anomalous negative shift of Vfb in several hundreds of mV irrespective of oxide thickness, which was enlarged by extending NO annealing duration [3]. This phenomenon is quite unexpected but would be explainable by assuming a dipole layer formation at the interface by SiC surface nitridation. Considering the polar Si-N bond formation with high density ~1014 cm2 at the interface, the SiC surface with Si-coordinated N atoms could introduce a dipole layer.SiO2/4H-SiC band alignment was investigated by two kinds of methods: the valence-band spectra analysis using x-ray photoelectron spectroscopy and the energy barrier height characterization of Fowler-Nordheim (F-N) current analysis. A clear trend was observed that the valence-band offset between 4H-SiC (0001) and SiO2 changes monotonically by the NO-POA durations to result in a increase of conduction-band offset at SiO2/SiC interface, which naturally explains the unexpected negative shift of Vfb observed in MOS capacitors. To our surprise, this trend appeared to the opposite direction for the gate stacks on 4H-SiC (000-1) or (1-100) fabricated with similar processes. For the MOS capacitors on (0001), we could clearly see a decreasing trend of F-N tunneling current by NO annealing duration which was attributable to the increase of conduction-band offset, while the opposite trend was observed for the capacitors on (000-1) and (1-100). Even though the defect-assisted conduction mechanisms such as Pool-Frenkel model appears to dominantly determine the temperature-dependence and electric-field-dependence of the leakage current at room temperatures or higher, obviously higher leakage current level for a given electric field was observed on (000-1) and (1-100) stacks than (0001), which should be attributable to the significant difference of the band alignment in several hundreds of mV. These results clarify that there are significant intrinsic difference of the gate leakage characteristics among SiC gate stacks on different crystal orientations, as well as the value of Vfb, explainable by the difference of band alignment.Next we examined a way to tune the Vfb of SiC gate stacks by the introduction of another dipole layer, by depositing of just a few nm-thick Al2O3 layer on top of SiO2 after NO-POA, based on the concept of oxide interface dipole layers reported for various high-k/SiO2 interfaces [4]. As a result we successfully demonstrated ~1V Vfb shift without a deterioration of interface state density only by Al2O3 deposition and post-deposition annealing. This technique is expected as a method not only to overcome the unexpected change of Vfb by nitrogen passivation process, but to achieve larger Vth without increasing the channel doping to avoid the deterioration of channel mobility.In conclusion, we found that nitrogen passivation of SiO2/4H-SiC gate stacks resulted in a significant change of band alignment to increase the conduction band offset on (0001) stack but to decrease the offset on (000-1) or (1-100) stacks, which results in a difference of gate leakage characteristics as well as Vfb. Control of the formation of dipole layers at SiO2/SiC interface and/or that formed in the multilayer dielectrics would have important roles to tune the band alignment of SiC gate stacks.[1] M. Noguchi et al., Jpn. J. Appl. Phys. 58, 031004 (2019).[2] J. Rozen et al., J. Appl. Phys. 105, 124506 (2009).[3] T. H. Kil and K. Kita, Appl. Phys. Lett. 116, 122103 (2020).[4] K. Kita and A. Toriumi, Appl. Phys. Lett. 94, 132902 (2009).

(Invited) Study on Impact of MOS Interface Passivation Processes on Band Alignment and Flat-Band Voltage of 4H-SiC Gate Stacks

Change of band alignment at SiO2/4H-SiC was observed by extending the duration of interface nitridation process to passivate the interface defects. The conduction-band offset on (0001) stack increases but that on (000-1) and (1-100) stacks decrease, which does not result only in a difference of flatband voltage (Vfb) but also in a difference of gate leakage characteristics among those stacks on different crystal faces. An introduction of an additional dipole layer in the gate stack was demonstrated by depositing a few-nm-thick Al2O3 on SiO2 to cause a positive shift of Vfb without degrading the quality of SiO2/SiC MOS interface. Control of those factors to cause Vfb shift is crucially important to reduce the mobility degradation in SiC MOSFET inversion channel by increasing the channel doping concentration to tune the threshold voltage.

Reliability of p-Type Pi-Gate Poly-Si Nanowire Channel Junctionless Accumulation-Mode FETs

In this study, p-type Pi-gate (PG) poly-Si nanowire channel junctionless accumulation-mode (JAM) field-effect transistors (FETs) were successfully fabricated and their reliability was investigated. The reliability of these PG JAM FETs was found to be dependent on the effective channel doping concentration (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> ). Through a negative gate bias stress (NGBS) test, we found that degradation in the average subthreshold swing (A.S.S.) and shift in the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) increases as the N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> of the PG JAM FETs decreases. Furthermore, the PG JAM FETs with a lower N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> show the more severe rate of deterioration in the transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) and ON current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ). By increasing N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch,eff</sub> to reduce the electric field ( E-field) on the gate oxide and tune the carrier transport mechanism in the poly-Si nanowire channel, a better immunity against the NGBS test in the p-type PG JAM FETs can be achieved under a gate overdrive voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GOD</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH,initial</sub> = -3.5 V) to perform the NGBS test.

Impact of Channel Doping Concentration on the Performance Characteristics and the Reliability of Ultra-Thin Double Gate DG-FinFET Compared with Nano-Single Gate FD-SOI-MOSFET by Using TCAD-Silvaco Tool

Impact of Channel Doping Concentration on the Performance Characteristics and the Reliability of Ultra-Thin Double Gate DG-FinFET Compared with Nano-Single Gate FD-SOI-MOSFET by Using TCAD-Silvaco Tool

Boosting the Performance of Liquid‐Gated Nanotransistor Biosensors Using Single‐Trap Phenomena

AbstractIn small‐area transistors, the trapping/detrapping of charge carriers to/from a single trap located in the gate oxide near the Si/SiO2 interface leads to the discrete switching of the transistor drain current, known as single‐trap phenomena (STP), resulting in random telegraph signals. Utilizing the STP‐approach, liquid‐gated (LG) nanowire (NW) field‐effect transistor biosensors have recently been proposed for ultimate biosensing with enhanced sensitivity. In this study, the impact of channel doping concentration on the capture process of charge carriers by a single trap in LG silicon NW structures is investigated. A significant effect of the channel doping concentration on the single‐trap dynamic is revealed. To understand the mechanism behind unusual capture time behavior compared to that predicted by the classical Shockley–Read–Hall theory, an analytical model based on the rigorous description of the additional energy barrier that charge carriers have to overcome to be captured by the trap at different gate voltages is developed. The enhancement of the sensitivity for single‐trap phenomena biosensing with an increase of the channel doping concentration is explained within the framework of the proposed analytical model. The results open prospects for the development of advanced single trap‐based devices.

Variability of DRAM Peripheral Transistor at Liquid Nitrogen Temperature

Dynamic random-access memory (DRAM) peripheral nMOSFETs with various channel length and channel doping concentration are analyzed at liquid nitrogen temperature (LNT). Important device parameters in circuit designs such as subthreshold mismatch, subthreshold swing (SS), transconductance, and drain-induced barrier lowering (DIBL) are analyzed at temperatures ranging from room temperature to LNT. In devices with relatively low channel doping, exacerbation of threshold mismatch at cryogenic temperatures is alleviated. Devices with lower doping exhibit better SS and transconductance characteristics. DIBL improved in short-channel devices at cryogenic temperatures, and the degradation of the DIBL with low doping is relatively small.

Total ionizing dose effects in junctionless accumulation mode MOSFET

In this paper, an extensive investigation of low-frequency (1/f) noise and total ionizing dose–response of junctionless accumulation mode double-gate (JAM DG) MOSFET is presented. Current–voltage (Id–Vg) characteristics and low-frequency noise of JAM DG MOSFET are simulated at different ionized doses and compared to different gate oxide thickness and different channel doping concentrations. A significant amount of irradiation-induced threshold voltage shift and increase in low-frequency noise is observed for different gate oxide thickness and channel doping concentration. Moreover, the irradiation-induced border trap densities are also obtained at different doses. The gamma radiation model of Sentaurus TCAD is used to get the required results.

Physical Parameter Variation Analysis on the Performance Characteristics of Nano DG-MOSFETs

DG-MOSFETs are the most widely explored device architectures for nano-scale CMOS circuit design in sub-50 nm due to the improved subthreshold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film (tsi by tsi- induced quantum confinement along with the confinement caused by a very high electric field at the interface. Therefore, quantum confinement effects on the device characteristics are also quite important and it needs to be incorporated along with short channel effects for nano-scale circuit design. In this paper, we analyzed a DG-MOSFET structure at the 20 nm technology node incorporating quantum confinement effects and various short channel effects. The effect of physical parameter variations on performance characteristics of the device such as threshold voltage, subthreshold slope, ION - IOFF ratio, DIBL, etc. has been investigated and plotted through extensive TCAD simulations. The physical parameters considered in this paper are operating temperature (Top), channel doping concentration (Nc), gate oxide thickness (tox) and Silicon film thickness (tsi). It was observed that quantum confinement of charge carriers significantly affected the performance characteristics (mostly the subthreshold characteristics) of the device and therefore, it cannot be ignored in the subthreshold region-based circuit design like in many previous research works. The ATLASTM device simulator has been used in this paper to perform simulation and parameter extraction. The TCAD analysis presented in the manuscript can be incorporated for device modeling and device matching. It can be used to illustrate exact device behavior and for proper device control.

Origin of the Low-Frequency Noise in the Asymmetric Self-Cascode Structure Composed by Fully Depleted SOI nMOSFETs

In this paper the origin of low-frequency noise in the Asymmetric Self-Cascode (A-SC) structure composed by Fully Depleted SOI nMOSFETs is investigated through experimental results. It is shown that the predominant noise source of the A-SC structure is linked to carrier number fluctuations, being governed by the noise generated in the transistor near the source. Larger channel doping concentrations degrade the quality of the Si-SiO2 interface and the gate oxide, which causes an increase of the normalized drain current noise spectral density, just as the reduction of the gate voltage overdrive, since there are few carriers in the channel. The A-SC structures have showed higher noise compared with single transistors. In saturation regime, the increase of the gate voltage overdrive has incremented the corner frequency, shifting the g-r noise to higher frequencies. Besides that, the normalized noise has been significantly increased when compared with the linear regime due to the rise of the drain current noise spectral density.

A +0.44°C/−0.4°C Inaccuracy Temperature Sensor With Multi-Threshold MOSFET-Based Sensing Element and CMOS Thyristor-Based VCO

A VCO-based(Voltage Controlled Oscillator) temperature sensor with multi-threshold MOSFET based sensing element is proposed. The proposed temperature sensor converts temperature variation into frequency and then into digital readings. In the proposed temperature sensor, the ratio of two reference currents, generated by P-MOSFETs operated in sub-threshold region and with different channel doping concentration, is used to sense the variation of temperature and achieves a $3\sigma $ inaccuracy of ±0.06°C after first-order poly-fit with systematic nonlinearity removal. The ratio of currents is then transformed into difference of the output frequencies of two identical CMOS-thyristor based VCOs, both of which are optimized to alleviate the impact of charge sharing and charge injection on the precision of the temperature sensor. In this way, there is no need for generating an external reference clock. The prototype is fabricated in a 130nm CMOS process and achieves an inaccuracy of +0.44°C/−0.4°C. The proposed sensor achieves a resolution of 0.1°C and a resolution FoM of 0.12nJ $\cdot \text{K}^{2}$ . The prototype occupies an area of 0.07mm2.

Explicit Threshold Voltage Modeling Insight for Short Channel Characterization of a WFE Elliptical GAA Strained-Si MOSFET

This paper presents explicit analytical modeling of a gate all around (GAA) strained silicon metal-oxide-semicondutor field-effect transistor (MOSFET) with elliptical cross section by incorporating the popular gate work function engineering (WFE) concept of lateral mole fraction variation from source to drain end. Surface potential and threshold voltage formulation of the proposed structure based on a quasi-three-dimensional scaling equation have been introduced. The derived model is further used to investigate the short channel characteristics of the device in terms of hot carrier effect (HCE), drain-induced barrier lowering (DIBL), threshold voltage roll off (TVRO), and subthreshold slope. The impact of device parameter variation including gate oxide thickness, effective radius, channel doping concentration, germanium (Ge) mole fraction variation in the strained silicon channel along with applied gate to source and drain biases are evaluated on device performance to justify its efficiency in comparison to its single gate material (SM) MOSFET equivalent. Our analytical analysis is further validated by ATLAS-3D device simulated data to verify the precision of the derived model.

Variation resilient reliable design of trigger pulse generator

This study presents a robust design of a trigger pulse generator that produces trigger pulses of variable widths/durations that are tuned using an external control as per the requirements. The proposed design comprises two elementary modules: a delay element and an XOR circuit. The proposed circuit is implemented using a 16 nm CMOS technology node and simulation results have been verified using the SPICE simulator. Various performance parameters such as power consumption, power delay-product, energy-delay product and impact of key circuit parameters [supply voltage (V DD), channel length (Lg), gate width (Wg), channel doping concentration (N A), oxide thickness (T OX), threshold voltage (V T) and carrier mobility (µ o)] on the duration of trigger pulses have been studied in-depth and performance parameters are compared with circuits already available in the literature. The proposed circuit produces trigger pulses of a minimum width of 191.3 ps at a nominal supply of 1.0 V with an average power consumption of 160 nW. The width of the trigger pulses can be varied from 191.3 to 457.2 ps using an external control from 1.0 to 0.7 V, respectively, at 16 nm technology node.

Vertically Stacked Gate-All-Around Structured Tunneling-Based Ternary-CMOS

This article proposes a novel structure for tunneling-based ternary-complementary metal-oxide-semi conductor (T-CMOS) to break through the power scaling constraints of conventional binary-CMOS. The previous T-CMOS uses off-leakage band-to-band tunneling (BTBT) currents generated at the deep drain-to-substrate junction for the third voltage state, which allows ternary inverter configuration with only two single transistors. However, the high-dose ion implantation for the BTBT layer must affect the channel doping concentration, leading to the threshold voltage fluctuation. To avoid the interference of the BTBT layer dopants to the channel as well as to maximize the electrostatic gate controllability, vertically stacked gate-all-around (GAA) field-effect transistor (GAAFET)-type T-CMOS device is proposed. By simply changing the ground plane (GP) doping concentration in existing GAAFET fabrication, the BTBT layer can be formed completely apart from the suspended channel layers. The changes of the transfer characteristics and the transient output voltage characteristics depending on the key parameters such as the GP doping concentration and the gate work function are thoroughly analyzed for the proposed GAA T-CMOS through mixed-mode TCAD device and circuit simulations. It is concluded that the two key parameters should be optimized, otherwise the margin for the third voltage state and the switching speed is seriously degraded.

Charge Based Current-Voltage Model for the Silicon on Insulator Junctionless Field-Effect Transistor.

In this study, we propose an accurate and simple current-voltage model for an SOI-JLFET based on a solution of the Poisson equation. The model is divided into three regions: accumulation, accumulation-depletion, and depletion. The charge density in each region is calculated with the Poisson equation and region-specific boundary conditions, and then the current is obtained by integrating the charge density with consideration of the Vds effect. The proposed model, which was implemented in HSPICE using Verilog-A, was validated using TCAD simulation for various physical conditions such as SOI channel thickness, gate oxide thickness, and channel doping concentration type. According to simulation results by the error rate calculation, our model shows more than 90% accuracy.

Analysis of D.C Parameters of Short-Channel Heterostructure Double Gate Junction-Less MOSFET Circuits Considering Quantum Mechanical Effects

In this article, the electrical behavior of short channel SiGe Heterostructure Junction-Less DG-MOSFET have been studied by incorporating the quantum mechanical effect and short channel effects. Analytical model and simulation result shows how the device process parameters like gate oxide thickness, silicon thickness, channel doping concentration, channel or gate length etc. have an impact on the D.C parameters like threshold voltage, surface potential. DIBL and threshold voltage of the nanoscale JL-MOSFET are also analyzed by considering the QME to raise the accuracy of the derived models. Extensive simulations are performed in SILVACO ATLAS TCAD tool to validate the proposed models. It is quite evident that the derived models and simulation results are in good agreement for a wide variation of process parameters. Schrodinger model has been used in ATLAS simulation platform to validate the derived analytical model considering QME. However, comprehensive analysis of the short channel SiGe Hetero-structure Junction-Less Double Gate Metal Oxide Semiconductor Field Effect Transistor gives a better view and understanding of D.C characteristics of the device. At the end, D.C characteristics (power dissipation, propagation delay, power-delay product) of an inverter circuit has been taken under consideration to check the impact of QMEs on circuit performance.

(Invited) Fundamentals and Process Technologies of Current Aperture Vertical Ga2O3 MOSFETs

Ga2O3 has exploded onto the semiconductor landscape for next-generation power electronics because its enticing material properties, most notably a large critical field strength stemming from its ultra-wide bandgap of 4.5 eV, promise miniaturized circuits and systems with high conversion efficiency. High-quality native substrates produced by melt-growth methods offer an economical platform to this technology. Ga2O3 transistors reported to date have predominantly taken on a lateral geometry, yet vertical switching devices are desirable for applications that demand high voltage ratings and high power levels since they allow for large current drives, simplified thermal management, and superior field termination. Capitalizing on cost-effective ion implantation technologies for shallow donor (silicon) and deep acceptor (nitrogen) doping of Ga2O3 with efficient dopant activation at a low thermal budget, we developed both depletion-mode (D-mode) [1] and enhancement-mode (E-mode) [2] current aperture vertical Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs).The vertical Ga2O3 MOSFETs were fabricated on low-doped (~1016 cm-3) halide vapor phase epitaxial drift layers grown on single-crystal β-Ga2O3 (001) substrates [3]. In these devices, silicon ion-implanted top source contacts were electrically isolated from the bottom drain contact by a nitrogen ion-implanted current blocking layer (CBL) [4] except at an aperture bounded by CBLs through which drain current was conducted. The CBL simultaneously served as a back-barrier for a top-gated lateral channel defined by another silicon ion implantation step. D-mode devices delivered a drain current density of 0.42 kA/cm2, a specific on-resistance of 31.5 mΩ·cm2, and an output current on/off ratio of over 108. E-mode devices, whose positive threshold voltage was attained by appropriately designing the channel doping concentration such that the channel was fully depleted at 0-V gate bias, showed a high output current on/off ratio of 2×107 despite a nonideal MOS interface that limited the maximum drain current density to <0.1 kA/cm2. Both D-mode and E-mode devices did not exhibit current collapse in pulsed measurements when subjected to off-state voltage stress; however, their hard breakdown occurred prematurely owing to leakage through the CBLs, a deficiency expected to be readily overcome with an optimized nitrogen implantation process. Further details regarding fabrication, performance, and physics of the devices, as well as potential directions for future development, will be discussed in the talk. The demonstration of planar-gate vertical Ga2O3 transistors based on a highly manufacturable all-ion-implanted process greatly enhances the prospects for Ga2O3-based power electronics applications.[1] M. H. Wong, K. Goto, H. Murakami, Y. Kumagai, and M. Higashiwaki, IEEE Electron Device Lett. 40, 431 (2019).[2] M. H. Wong, H. Murakami, Y. Kumagai, and M. Higashiwaki, Proc. 77th Device Research Conference (2019).[3] H. Murakami, K. Nomura, K. Goto, K. Sasaki, K. Kawara, Q. T. Thieu, R. Togashi, Y. Kumagai, M. Higashiwaki, A. Kuramata, S. Yamakoshi, B. Monemar, and A. Koukitu, Appl. Phys. Express 8, 015503 (2015).[4] M. H. Wong, C.-H. Lin, A. Kuramata, S. Yamakoshi, H. Murakami, Y. Kumagai, and M. Higashiwaki, Appl. Phys. Lett. 113, 102103 (2018).

Compact Modeling of Graded N-Channel Independent Gate FET with Underlaps, Spacer and S/D Straggle for Low Power Application

This paper presents an analytical modeling of a separated gate underlap graded N-channel FET to assess the short-channel effects. A 2D modeling scheme is employed to derive its surface potential, threshold voltage, subthreshold current and DIBL. The proposed structure includes four regions, and the potential function for each region is developed from solution of Poisson’s Equation using appropriate approximations. In order to estimate surface potential of the device, parabolic approximation scheme with geometrical approach is used in channel region to cater the influence of independently biased gates, while in source/drain underlap regions, conformal mapping is employed for the fringing field estimation. The study suggests that the independent gate bias, channel doping concentrations, spacer and other device parameters viz. underlap length, gate work function, gate oxide thickness etc. are efficacious in modulating the threshold voltage, subthreshold current and DIBL. The analytical results are compared with those obtained from TCAD device simulator, and found to match very closely. Moreover, the analytical solutions also follow the similar nature of variations as appeared in other experimental reports.

Models of Threshold Voltage and Subthreshold Slope for Macaroni Channel MOSFET

Models of threshold voltage and subthreshold slope (SS) for macaroni channel MOSFET are built for the first time based on the potential model in our previous work. These models clearly illustrate the variations of threshold voltage and subthreshold slope caused by short-channel-effects when changing gate length, silicon thickness, oxide thickness, channel doping concentration, and drain-to-source bias. The good agreements between simulations and models verified the validity of those models.

Germanium-Tin Junctionless p-Finfets: Effects of Channel Doping Concentration and Fin Width

High-mobility channel materials are important to extend the CMOS technology to beyond 3-nm node. GeSn p-MOSFETs with a record-high hole mobility of 845 cm2/V-s and a high drive current of > 1850 A/m were demonstrated [1, 2]. While the high-performance GeSn p-FETs were demonstrated, the required complicated fabrication steps remain challenging. A junctionless (JL) FinFET device was proposed to suppress the short-channel effects with easier fabrication steps [3]. Furthermore, for the JL devices, there are no additional ion implantation or annealing steps for the S/D formation, which can prevent Sn segregation or strain relaxation. While the device performance of JL FinFETs can be enhanced by increasing the channel doping concentration, the electrostatic control over the bulk channel in a JL FinFET becomes worse. In this work, we address the effects of the fin width and doping concentration on the device performance of GeSn JL FinFETs. GeSn JL p-FinFETs with fin widths of 10–50 nm are fabricated (Fig. 1 (a)). High-quality p-GeSn films were epitaxially grown on silicon-on-insulator substrates by in-situ doping chemical vapor deposition (CVD) and . HR-XRD results showed that the Ge0.92Sn0.08 layer was fully strained to the underlying relaxed Ge layer with clear Pendellösung fringes around the GeSn peak. Excellent crystallinity and defect-free GeSn/Ge interface can be observed in TEM images. The carrier density and mobility were characterized by Hall measurements. Boron dopants were fully activated up to the level of 1.3 × 1019 cm-3. The device fabrication steps were carried out at temperatures below 400 ◦C to prevent the Sn segregation. After a post-metal annealing step, the drive current was boosted by a factor of 1.5 due to the reduction of the contact resistance by the NiGeSn formation (Fig. 1 (b)). Furthermore, the SS was also improved after the PMA step. To improve the device performance of JL FinFETs, the doping concentration in the GeSn channel was increased by in-situ CVD. The drive current increases with the doping concentration due to the larger channel conductivity (Fig. 1 (c)). Benefiting from the low-temperature processes, JL structure, and the narrow fin width, the best SS is 88 mV/dec and extremely high Ion/Ioff ratios of 105 and 107 were achieved for the overdrive voltages of 0.7 V and 2 V, respectively (Fig. 1 (d)). Last, TCAD simulations were performed to investigate the effects of the channel doping concentration, the fin width, and the defect density at the oxide interface on SS. While for a high performance GeSn JL FinFET, the doping level was increased, the channel cannot be shut off effectively, leading to a higher subthreshold leakage and a poorer SS. To effectively deplete the carriers in the channel, a much reduced fin will be required. While shrinking the devices could improve the SS, the simulation results suggest that reducing the defect density at the high-k/GeSn interface is also crucial for further performance improvements of the GeSn JL FinFETs. [1] M. Liu et al., VLSI Symp. Tech. Dig., Jun. 2014. [2] Y.-S. Huang et al., IEDM Tech. Dig., Dec. 2017. [3] J. Colinge et al., Solid-State Electron., vol. 65, pp. 33–37, Nov. 2011. Figure 1