Compact Modeling of Graded N-Channel Independent Gate FET with Underlaps, Spacer and S/D Straggle for Low Power Application

Abstract

This paper presents an analytical modeling of a separated gate underlap graded N-channel FET to assess the short-channel effects. A 2D modeling scheme is employed to derive its surface potential, threshold voltage, subthreshold current and DIBL. The proposed structure includes four regions, and the potential function for each region is developed from solution of Poisson’s Equation using appropriate approximations. In order to estimate surface potential of the device, parabolic approximation scheme with geometrical approach is used in channel region to cater the influence of independently biased gates, while in source/drain underlap regions, conformal mapping is employed for the fringing field estimation. The study suggests that the independent gate bias, channel doping concentrations, spacer and other device parameters viz. underlap length, gate work function, gate oxide thickness etc. are efficacious in modulating the threshold voltage, subthreshold current and DIBL. The analytical results are compared with those obtained from TCAD device simulator, and found to match very closely. Moreover, the analytical solutions also follow the similar nature of variations as appeared in other experimental reports.