Load Current Changes Research Articles

Air-flow control in fuel cells using delay-based load governor and feedforward augmented dynamic inversion

The frequent and sudden increase of load in electric vehicles depletes oxygen from the fuel cell cathode, leading possibly to oxygen starvation. This paper presents the design of an air flow controller for fuel cell systems (FCS) that aims to replenish the depleted oxygen. A dynamic inversion is used as the feed-forward compensation for the disturbance effect coming from the load current change. However, the inverted dynamics have negative relative degree (improper) and not physically realizable. To make it proper, an augmentation by delay is done, with the same delay added into demand current. The current-dependent time delay introduced in the demand current gives the FCS the opportunity to prepare a sufficient air flow that can withstand the dip in oxygen excess ratio (OER). Besides, the FCS plant is linearized at various operating points, and the dynamic feedforward controller is designed at several operating points with interpolation applied for in-between values. The simulation results show a considerable improvement in the OER response where the constraint is met and the recovery time is reduced.

0.5–1-V, 90–400-mA, Modular, Distributed, 3 × 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation

This article presents on-chip power delivery hardware comprised of nine event-driven (ED) digital low-dropout voltage regulators (LDOs) for a large digital load. The goal is to address the performance degradations in an LDO's accuracy and dynamic load regulation in the presence of parasitics in the power grid of a load. In particular, we investigate the effects of power grid resistance ( R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ), which becomes worse with the size of a digital load and technology scaling. Two critical problems that we address are: 1) the IR drop and 2) the dynamic voltage droop problems. Employing multiple LDOs across the power grid improves the IR drop for mainly better voltage sensing. To tackle the voltage droop problem, we distribute LDOs with ED control such that the LDO closest to a localized droop can instantly correct it. To further improve the feedback control latency, we also enhance each LDO with a novel domino sampling and regulation technique. We prototype the on-chip power delivery system consisting of 3 ×3 digital LDOs in a 65-nm CMOS. We also devise the framework to analyze the stability of the multi-LDO system across R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> values. Measurements show that at 0.5-V (1 V) input, the single LDO exhibits 49.8-mV (94.1 mV) voltage droop for a load current change of 4.04 mA/0.1 ns (13.8 mA/0.2 ns) with a 0.1-nF integrated output capacitor. Also, the nine-LDO system achieves a current density of 248.8 mA/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (1.118.6 A/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) at 0.5-V (1 V) input voltage.

Study on the influence of current on 500 kV AC marine cable based on numerical simulation

Due to the extremely complex changes in marine environmental factors and frequent changes in the actual load current of the submarine cable, it is necessary to analyze and study the mechanical and thermal characteristics of the high-voltage submarine cable system under different conditions to ensure the reliability of the power transmission performance of the submarine cable. In this paper, the finite element model is adopted to study the physical parameters of the submarine cable, taking burial depth, ambient temperature, and current as dependent variables. Some of the parameters related to the environment refer to the ocean currents near Zhoushan, and the model bases on the actual current and temperature data of the 500 kV AC submarine cable. The results show that in order to increase the load capacity of the submarine cable and reduce the thermal strain of the submarine cable, the heat dissipation of the submarine current should be increased, so the buried depth should be appropriately reduced. After the ambient temperature rises, in order to reduce the loss of electric energy and cable deformation, the carrying current should be reduced moderately. The research carried out a simulation based on the actual physical parameters of each layer of the submarine cable and predicted the changes in the submarine cable in Zhoushan with different current carrying capacity in different seasons, so it has reference significance in actual engineering applications.

A New Improved V-Square-Controlled Buck Converter With Rail-to-Rail OTA-Based Current-Sensing Circuits

The converter proposed in this article is a new improved voltage-square buck converter using a rail-to-rail OTA-based current-sensing circuit. This circuit architecture used a constant on-time modulation mode and uses a rail-to-rail OTA-based inductor-current-sensing circuit to form a current feedback path. The rail-to-rail OTA-based current sensor has wide input range, so it can be directly connected to both the ends of the inductor. Then, a voltage loop is added to achieve fast transient response and reduce the output voltage ripple. Therefore, the proposed voltage-square buck converter responses to load current change immediately by two voltage and one current feedback signals. The converter is implemented with TSMC 0.35- $\mu \text{m}$ CMOS 2P4M process, and the chip area is 2.24 mm.2 The input voltage range is 3–3.6 V. When the output voltage is 2.5 V and the output current is 350 mA, the circuit has the maximum efficiency of 91%. The contributions of this article are listed in the following: 1) we have proposed a new improved $V^{2}$ control architecture of power converters, which combined current-mode control and voltage-mode control; 2) the proposed architecture has one current control loop and two voltage control loops, which can balance the output voltage and output current; 3) the proposed converter has the characteristics of faster transient response and lower transient voltage; 4) we designed, measured, and implemented this proposed converter; and 5) from the FOM formula, the performance of the proposed converter is found to be better than other recent works.

Adaptive On-Time Buck Converter with Wave Tracking Reference Control for Output Regulation Accuracy

A ripple-based constant on-time (RBCOT) buck converter with a virtual inductor current ripple (VICR) control can relax the stability constraint of large equivalent series resistance (ESR) at an output capacitor, but output regulation accuracy deteriorates due to the issue with output DC offset. Thus, this paper proposes a wave tracking reference (WTR) control to improve converter stability with low ESR and concurrently eliminate output DC offset on the regulated output voltage. Moreover, an adaptive on-time (AOT) circuit is presented to suppress the switching frequency variation with load current changes in continuous conduction mode. A prototype chip was fabricated in 0.35 µm CMOS technology for validation. The measurement results demonstrate that the maximum output DC offset is 4.1 mV and the output voltage ripple is as small as 3 mV. Furthermore, the switching frequency variation with the AOT circuit is 11 kHz when load current changes from 50 mA to 500 mA, and the measured maximum efficiency is 90.9% for the maximum output power of 900 mW.

Development of ripple reduced solar photovoltaic regulators using boomerang sliding mode control strategy

SummaryDC–DC boost converters are extensively used in wide range of solar photovoltaic (PV) applications. A common problem in PV regulator is the presence of ripples in output voltage and output current, due to the oscillations in PV power, inaccurate switching, and inadmissible inductor peak currents. In general, conventional boost converters are widely used in PV regulator; however, conventional PWM‐controlled boost converters are upgraded to sliding mode controller (SMC)‐based PWM controllers, which has been elaborated in the literature. However, SMC‐based boost converter experiences the following problems: (i) presence of ripples in the output current and (ii) dynamic instability during sudden change in load current. This paper addresses the aforementioned problems and proposes a boomerang trajectory‐based SMC (BT‐SMC) control strategy for ripple mitigation in conventional DC–DC boost converters specifically used in PV regulator. BT‐SMC tracker tracks the reference wave shape and controls the duty cycle, with respect to the switching frequency to have a ripple mitigated output. This self‐adapting system provides an adequate reduction in ripples and rapid convergence of error nearest to zero. A detailed analysis on switching frequency transition, load variation, trajectory control, and its stability existence is conducted, and the proposed system is implemented using dSPACE‐MicroLabBox‐DS1202.

A Fast-Transient Low-Dropout Regulator With Current-Efficient Super Transconductance Cell and Dynamic Reference Control

A fast-transient, current-efficient low-dropout regulator (LDO) with super transconductance cell (STC) is proposed in this paper. By adopting advanced current amplifier (CA) and dynamic biasing (DB) techniques for the error amplifier (EA), the feedback loop bandwidth can be significantly extended without increasing much quiescent power, which reduces output voltage spikes and response time greatly. Moreover, dynamic reference control (DRC) with robust loop stability is embedded in the LDO to adaptively adjust voltage reference during transient so as to further enhance the slew rate of EA, realizing significant enhancement for the transient performances. This circuit has been implemented in a 0.35μm CMOS process and occupies an active chip area of 456×278 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>2</b></sup> . Experimental results show that it is able to provide 100mA load current at 200mV dropout voltage, with current efficiency of 99.88%. The output voltage spike under maximum load current change in 20ns edge time is less than 11.2mV with a 0.054μs response time. The power-supply rejection (PSR) at 100kHz is -75.6dB.

Design of Capacitor-less LDO applied to Low Power Supply with High-precision Bandgap

This paper proposes a capacitor-less low dropout regulator (LDO) applied to low power supply to meet the needs of low power consumption and highly integration. In order to improve the transient response of the system, a dynamic bias circuit is designed, which can automatically track the change of load current. In addition, the temperature coefficient of bandgap reference in conventional LDO is generally 20-100 ppm/°C. The bandgap reference circuit proposed in this paper can achieve 1.73 ppm/°C without trimming, and the accuracy is better than 1% at all process corner. The design and simulation are based on TSMC 0.18 μm CMOS process, the simulation results show that the LDO output voltage is 1 V when input power supply voltage is 1.2 V. The proposed regulator can operate with a minimum dropout voltage of 200 mV when load current is 50 mA. The maximum undershoot and overshoot voltages are 34 mV and 28 mV, respectively, with 1mA-50mA and 50mA-1mA step load current.

Weak Grid Integration of a Single-Stage Solar Energy Conversion System With Power Quality Improvement Features Under Varied Operating Conditions

A three-phase single-stage solar energy conversion system (SECS) integrated into a weak distribution network is presented. The grid integration and maximum power point operation of the photovoltaic (PV) array are achieved by a voltage source converter. The SECS is capable of feeding distortion-free and balanced grid currents with power factor correction, even at adverse grid side, PV array side, and load side operating conditions. The integration of SECS into the weak grid having distorted, unbalanced, and varying grid voltages is achieved while maintaining the power quality. The dc offset introduced in the sensed grid voltages is also effectively eliminated. For swift system response to changes in load currents, their fundamental weights are swiftly extracted. In the absence of solar irradiance, the power is imported from the utility to supply the local loads, and the system continues to execute its power quality improvement functions. In case of loss of PV power or large voltage deviations, the dc-link voltage is adaptively varied according to the grid voltage changes, increasing system reliability, and reducing operating losses. The efficacy of the SECS is validated through test results at different operating scenarios.

An Improved Fast-Transient-Response Low-Transient-Voltage Boost Converter With Pseudo-Current Hysteresis-Controlled Techniques

This paper proposes a new and improved fast-transient-response low-transient-voltage boost converter with pseudo-current hysteresis-controlled techniques (PCHC). The converter uses the rail-to-rail current-sensing circuit to provide a hysteresis-controlled signal, helping to speed up the transient response and improve the overall efficiency. The proposed boost converter has been fabricated with TSMC $0.18~\mu \text{m}$ CMOS 1P6M technology, and the chip area is $1.18\times 1.18$ mm2 (include PADs). The measured results show that the input voltage range is from 0.5 V to 1 V, the output voltage is set as 1.8 V, and the output load current range is from 10 mA to 100 mA. When the output load current changes from 10 mA to 100mA and 100 mA to 10 mA, the transient responses are both 2 $\mu \text{s}$ , and peak power efficiency is 88.5% at the output load current of 75 mA.

An Analog-Assisted Digital LDO With Single Subthreshold Output pMOS Achieving 1.44-fs FOM

This letter describes an analog-assisted digital LDO that cascades a conventional digital LDO structure with a single, large output pMOS biased in subthreshold to enable fast response to output voltage droop. By digitally controlling the gate voltage of the output pMOS, the operating regime of the output transistor is decoupled from the input voltage. In addition, a 2-pF capacitor between the output voltage and the gate of the output pMOS creates a high-pass path to boost the output current when voltage droops occur. The proposed design is fabricated in 28-nm CMOS, and it enables a uniform transient response over an input voltage range of 0.5-0.9 V. The measured voltage droop when load current changes from 10 to 60 mA (1-ns edge time) is 110 mV at input voltages of both 0.5 and 0.9 V, resulting in a speed FOM of 1.44 fs.

A Novel Boost-Buck Converter Architecture for Improving Transient Response and Output-Voltage Ripple

Buck-boost converters are widely used in the development of DC-DC converters. Several techniques and algorithms have been introduced to improve the transient response of buck-boost converters. However, due to the opposite trends of the output current change and the output voltage change, undershoot or overshoot in the output voltage still seems to be inevitable. In order to overcome this problem, a novel boost-buck converter architecture is proposed to build a fast transient response DC-DC converter. The converter consists of a cascaded configuration of the boost and buck stages. The boost stage converts the input voltage to the shared capacitor voltage and the buck stage supplies energy to the load by converting the shared capacitor voltage to the output voltage. By harnessing the energy stored in the shared capacitor, the transient response of the boost buck converter can be improved to 2 µs in a step-up load current change of 1 A with an output-voltage ripple of 15 mV.

Multivariable Unconstrained Pattern Search Method for Optimizing Digital PID Controllers Applied to Isolated Forward Converter

Most of the traditional PID tuning methods are heuristic in nature. The heuristic approach-based tuned PID controllers show only nominal performance. In addition, in the case of a digital redesign approach, mapping of the heuristically-designed continuous-time PID controllers into discrete-time PID controllers and in case of the direct digital design approach, mapping of the continuous-time plant (forward converter) into the discrete-time plant, results in frequency distortion (or warping). Besides this, nonlinear elements such as ADC and DAC, and delay in the digital control loop deteriorate the control performance. There is a need to tune conventionally-designed digital controllers to enhance performance. This paper proposes optimized discrete-time PID controllers for a forward DC–DC converter operating in continuous conduction mode (CCM). The considered conventional digital PID controllers designed on the basis of the digital redesign and direct digital approaches are tuned by one of the multivariable unconstrained pattern search methods named Hooke–Jeeves (H–J) search method to ensure excellent output voltage regulation performance against the changes in input voltage and load current. Numerical results show that the H–J-based optimized PID compensated forward converter system shows tremendous improvement in performance compared to its unoptimized counterpart and simulated annealing (SA)-based compensated system, thus justifying the applicability of the H–J method for enhancing the performance.

Small Signal Modeling and Control Loop Design of Critical Conduction Mode Active Clamp Flyback Converter

Critical conduction mode (CrCM) active clamp flyback (ACF) converter is regarded as a good candidate to be applied in high-frequency small power supplies. This article focuses on the modeling, analysis, and controller design of CrCM-ACF converter. The small signal model of the converter is derived based on a zero-input resonant equivalent circuit and extended describing function (EDF) method for the first time, then the obtained full-order model is simplified to a low-order model. This procedure establishes an insightful understanding about the effects of the converter parameters and working conditions. Based on the simplified model, a control loop compensator is designed in a single-loop voltage-feedback control scheme for high dynamic performance. An experimental prototype of digital controlled CrCM-ACF converter is built, the accuracy of the derived model is verified by comparing with experimental and simulation results. The performance of the compensator is experimentally evaluated by applying abrupt load current and reference voltage changes in the operating conditions of the converter. From the experimental results, it is demonstrated that the derived analytical model and designed compensator are effective in regulating the output voltage in CrCM-ACF converter.

Mathematical modelling of physical processes in a synchronous generator with permanent magnets for output voltage stabilization circuits

When some consumers are powered from independent sources of electric energy, there is needed stabilization of output voltage on the generator in a wide range of load current changes. The use of traditional stabilization methods in the power supply systems with electric machines does not always provide the required level of the supply voltage. The use of synchronous magnetoelectric generators in voltage stabilization circuits is of particular interest in this regard. For determining the possibility of their use, the operating conditions of electric machines were analyzed, the main factors affecting their external characteristics when varying the load level were identified. The studies were based on the mathematical model that ultimately made it possible to obtain dependences convenient for use in engineer.

Study on the test method of rapid change of load current of intelligent electricity meters

With the continuous changes of the working environment of the electric energy meter, the dynamic detection method of the electric energy meter becomes more and more important. Therefore, in recent years, the IEC 62052-11 Standards Committee has proposed to add a rapid change test of electric energy meter load current. This article proposes an effective dynamic test method according to the requirements of this regulation standard, builds an electric energy meter dynamic error test platform and develops a software test system. An anti-submarine mechanism is proposed for the electric energy measurement algorithm of the smart meter, and the load current rapid change test of various electric energy meters from different manufacturers at home and abroad is tested, and the correctness of this test method is verified.

An Improved Optimum-Damping Current-Mode Buck Converter With Fast-Transient Response and Small-Transient Voltage Using New Current Sensing Circuits

This article presents an improved optimum damping current-mode buck converter with fast-transient response and small-transient voltage using new current sensing circuits. The improved optimum-damping circuit, consisting of the dynamic slope generator and the proposed rail-to-rail current sensor, can stabilize the converter during the output current change and can accelerate the transient response to achieve better figure of merit performance. The dynamic slope generator can compensate the slope to prevent subharmonic oscillation issue and lower undershoot/overshoot without an extra slope compensator. The proposed rail-to-rail current sensor increases the input voltage range, accurately captures the inductor current information, and accelerates the transient response as the load current changes, because it eliminates spikes without the need for a sample-and-hold circuit in a conventional current-sensing circuit. The contributions of the proposed converter are listed in the following: 1) we have proposed a new current-sensing circuit without voltage divider, which can be operated rail-to-rail and improve the dynamic response; 2) the new current-sensing circuit consisted of no switches and therefore, without switching noises; 3) the new current-sensing circuit without voltage divider has a smaller chip area and a smaller path delay; 4) the proposed current-sensing circuit needs no sample-and-hold circuits to reduce current spikes; 5) the transient response and transient voltage of the proposed converter are better than others' works; and 6) we have designed and implemented a new optimum-damping current-mode buck converter with better performances compared with previous publications.

A Current-Mode-Hysteretic Buck Converter With Constant-Frequency-Controlled and New Active-Current-Sensing Techniques

This article presents a hysteretic-current-controlled buck converter with constant-frequency-controlled and active-current-sensing (ACS) techniques. This converter used phase-frequency-locked techniques to achieve constant switching frequency. Even if the input voltage or output load current changes, the switching frequency will be as stable as possible at 1 MHz. The proposed ACS circuit will not generate sparks, so the current feedback loop does not need a sample-and-hold circuit, and that will reduce the transient response time. The proposed buck converter has been fabricated with TSMC 0.35 μm CMOS 2P4M technology; the total area of the chip is 1.5 mm × 1.5 mm. The measurement results of this buck converter show that the maximum power efficiency is 90% when the output voltage is 2.5 V and the load current is 300 mA. The output voltage range is 2.5-1 V, and the maximum load current is 600 mA. When the load current varies between 100 and 500 mA, the load transient response is 2.6 μs/2.2 μs and undershoot/overshoot is 20 mV/30 mV. The switching frequency of this buck converter is locked at 1 MHz and the voltage error is within 1%.

Low-Power Area-Efficient LDO With Loop-Gain and Bandwidth Enhancement Using Non-Dominant Pole Movement Technique for IoT Applications

A new Low Drop-Out (LDO) voltage regulator with off-chip capacitor for low power applications is presented. The LDO takes advantage of non-dominant pole movement technique to improve loop-gain and Unity Gain Frequency (UGF). Tangible improvements were obtained while supporting a large load capacitor and low-power consumption. The proposed LDO 1) consumes low quiescent current (47.3% current efficiency (CE) at 10 μA load current bias circuit inclusive), 2) is area-efficient (no multi-gain amplifiers), and 3) enjoys a short response time in the active-mode with its adaptive bandwidth expansion and loop-gain enhancement technique, while 4) maintaining 99.94% CE in the full-load condition. A prototype chip with TSMC 180 nm CMOS technology was fabricated for detailed characterisation. The measured output voltage of the LDO was 1.65 V with 1.8 V input, consuming 11 μA quiescent current including the bias circuit current. The load regulation was 10 mV when load current changes from 30 nA to 50 mA with fall and rise time of 10ns.

A 65nm 0.6–1.2V Low-Dropout Regulator Using Voltage-Difference-to-Time Converter With Direct Output Feedback

This brief proposes a fully integrated output capacitor-less low-dropout regulator (LDO) using a voltage difference to time converter (VDTC). Proposed dynamic amplifier based VDTC allows low voltage operation and significantly reduces the quiescent current. The linear characteristics of VDTC result in output ripple-less operation and good regulation performance. Using direct output feedback through a small coupling capacitor, the gate voltage of the power transistor is instantly compensated to mitigate fluctuation of the output voltage when a sharp load transient occurs. Fabricated in 65 nm LP CMOS, the proposed LDO demonstrates a wide operation range with an input voltage range of 0.6-1.2 V and a load current of over 30 mA across all voltages without an output capacitor. With reduced output impedance due to direct output feedback, the measured undershoot is 158 mV, which is recovered in 9.6 μs, when the load current changes by 28 mA in 1 ns. The peak current efficiency is more than 99.99% and the figure of merit (FOM) is 0.202 fs. The active area of the control block is 0.002 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .