Cellular Processor Research Articles

Convolutional kernel function algebra

Many systems for image manipulation, signal analysis, machine learning, and scientific computing make use of discrete convolutional filters that are known before computation begins. These contexts benefit from common sub-expression elimination to reduce the number of calculations required, both multiplications and additions. We present an algebra for describing convolutional kernels and filters at a sufficient level of abstraction to enable intuitive common sub-expression based optimizations through decomposing filters into smaller, repeated, kernels. This enables the creation of an enormous search space of potential implementations of filters via algebraic manipulation. We demonstrate how integral image and sliding window optimizations can be expressed in the context of common sub-expression elimination as well as show the direct use case for this algebra in massively SIMD multiply-free contexts such as in cellular processor arrays. We then show that this algebra is general enough to express and optimize kernels that use non-standard semi-rings to enable shortest path algorithms.

How can Waddington-like landscapes facilitate insights beyond developmental biology?

The Waddington landscape has offered an intuitive framework to conceptualize cell fate, grounded in our innate understanding of the physical rules that guide balls rolling down a hill. The hills and valleys of the landscape are molded by the cellular processor—the inner regulatory network of DNA, RNA, and proteins that govern cell “state” —and microenvironmental inputs are forces that guide cells in their probabilistic journey down the hill. While a powerful visual, it’s time we break out from the confines of this imaginary landscape.

Context-aware synthetic biology by controller design: Engineering the mammalian cell.

The rise of systems biology has ushered a new paradigm: the view of the cell as a system that processes environmental inputs to drive phenotypic outputs. Synthetic biology provides a complementary approach, allowing us to program cell behavior through the addition of synthetic genetic devices into the cellular processor. These devices, and the complex genetic circuits they compose, are engineered using a design-prototype-test cycle, allowing for predictable device performance to be achieved in a context-dependent manner. Within mammalian cells, context effects impact device performance at multiple scales, including the genetic, cellular, and extracellular levels. In order for synthetic genetic devices to achieve predictable behaviors, approaches to overcome context dependence are necessary. Here, we describe control systems approaches for achieving context-aware devices that are robust to context effects. We then consider cell fate programing as a case study to explore the potential impact of context-aware devices for regenerative medicine applications.

Cellular processors in multichannel image classifiers

The purpose of the work is to analyze multichannel images used in medical research related to the classification of radiographs. Classification rules for the bitmap multichannel images are based on two methods of the descriptors formation. Through these descriptors, two groups of classifiers are built with the subsequent aggregation of solutions. In channels with high image spatial resolution the descriptors are formed based on the analysis of border contours of the corresponding bitmap segments. To analyze and classify the selected contours, the bitmaps in channels with high resolution in the spatial frequency range or in the electromagnetic spectrum are used. The use of multiscale windows in each channel allows creating multiple classifiers for one channel with the subsequent aggregation of solutions both within the channel and between the channels. This results in a network structure of classifiers (cellular classifiers), which parameters are determined through training, based on expert assessments or hybrid methods. The result of the research is the development of efficient algorithms for processing and analyzing multichannel images. The authors determine the models’ structure based on cellular processors using neural networks. Those structures can be adapted to specific features of the image and allow implementing the objects’ classification in medical images in real time. The conclusions are drawn about the possibility of applying the method to building an intelligent decision-making system for all types of processed multichannel bitmap images.

Low power high-performance smart camera system based on SCAMP vision sensor

Vision sensors based upon pixel-parallel cellular processor arrays offer the unique opportunity to realise high-performance, flexible, low power image processing systems. By virtue of processing on the focal-plane, the energy-demanding requirement to digitize a captured frame's raw pixel data is reduced, with returned data constituting only that which is salient. We describe a stand-alone vision system incorporating a SCAMP-3 vision chip, an FPGA and an ARM Cortex-M3 microcontroller. SCAMP integrated circuits operate as SIMD computers; each pixel incorporating a compact but powerful analogue processor and local memory, with all operations occurring in parallel over the 128x128 array. Algorithms are developed to operate natively upon the focal-plane as far as possible, with additional serial and higher-level operations occurring on the microcontroller. The power consumption of the system is algorithm-dependent. An algorithm developed for loiterer detection at 8fps has been shown to consume an average power of 5.5mW, with a more complex object tracking and counting system consuming 29mW.

Topographic implementation of particle filters on cellular processor arrays

Particle filters are a state-of-the-art method for the state estimation of non-linear stochastic systems. Recent many-core architectures and cellular processor arrays offer a new paradigm for algorithm development, which provides not only high performance, but also theoretical advances for parallel implementations. We have developed a new variant of the particle filter algorithm, which suits ideally implementation on a cellular processor array. The new algorithm often performs better than the classical one and a significant gain in running time can be achieved, especially when there is a large number of particles to be simulated.

Split and shift methodology on cellular processor arrays: area saving versus time penalty

ABSTRACTThis paper addresses the so‐called split and shift methodology. This methodology deals with the implementation of kernels of sizes that go above the physically implemented resources (local connections and weighting circuits) on synchronous cellular processor arrays (CPA), including the realization of large neighborhood operations and/or the reduction of the available hardware in order to drop the area consumption. Two main goals are pursued in the development of the methodology, namely: (1) minimum penalty at processing time and (2) absolutely no penalty at functional level. The paper presents different techniques and guidelines for the methodology application and introduces a Figure of Merit to evaluate them by relating area gains with time penalty. This, along with a kernel shape analysis, led us to propose more adequate configurations of weighting circuits and to justify the classical choice of North‐East‐West‐South connectivity. To validate the methodology, we realize several estimates over actual physical implementations, and we propose the realization over CPAs of the spin filters, scale invariant feature transform and speeded‐up robust features algorithms. A more in‐depth trade‐off analysis is realized over the implementation of the pixel level snakes algorithm. Copyright © 2012 John Wiley & Sons, Ltd.

Proteolysis-induced N-terminal Ectodomain Shedding of the Integral Membrane Glycoprotein CUB Domain-containing Protein 1 (CDCP1) Is Accompanied by Tyrosine Phosphorylation of Its C-terminal Domain and Recruitment of Src and PKCδ

CUB-domain-containing protein 1 (CDCP1) is an integral membrane glycoprotein with potential as a marker and therapeutic target for a number of cancers. Here we examine mechanisms regulating cellular processing of CDCP1. By analyzing cell lines exclusively passaged non-enzymatically and through use of a panel of protease inhibitors, we demonstrate that full-length 135 kDa CDCP1 is post-translationally processed in a range of cell lines by a mechanism involving serine protease activity, generating a C-terminal 70-kDa fragment. Immunopurification and N-terminal sequencing of this cell-retained fragment and detailed mutagenesis, show that proteolytic processing of CDCP1 occurs at two sites, Arg-368 and Lys-369. We show that the serine protease matriptase is an efficient, but not essential, cellular processor of CDCP1 at Arg-368. Importantly, we also demonstrate that proteolysis induces tyrosine phosphorylation of 70-kDa CDCP1 and recruitment of Src and PKCdelta to this fragment. In addition, Western blot and mass spectroscopy analyses show that an N-terminal 65-kDa CDCP1 ectodomain is shed intact from the cell surface. These data provide new insights into mechanisms regulating CDCP1 and suggest that the biological role of this protein and, potentially, its function in cancer, may be mediated by both 70-kDa cell retained and 65-kDa shed fragments, as well as the full-length 135-kDa protein.

Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image-processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low-power consumption. An integrated circuit with proof-of-concept array of 24×60 cells has been fabricated in a 0.35µm three-metal CMOS process and tested. Occupying only 16×8µm2 the binary wave-propagation cell is designed to be used as a co-processor in general-purpose processor-per-pixel arrays intended for focal-plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation

A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations, reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A 32 × 32 cell parallel analog test array for reference-shift with a maximum block-size of 16 × 16, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 µm CMOS technology.

Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing

This paper presents an FPGA realisation of an application-specific cellular processor array designed for asynchronous skeletonization of binary images. The skeletonization algorithm is based on ite...

DENDRITIC CELL BASED VACCINES: PROGRESS IN IMMUNOTHERAPY STUDIES FOR PROSTATE CANCER

No effective treatment is currently available for metastatic prostate cancer. Dendritic cell (DC) based cancer vaccine research has emerged from the laboratories to human clinical trials. We describe progress in the development of DC based prostate cancer vaccine. The literature was reviewed for major contributions to a growing number of studies that demonstrate the potential of DC based immunotherapeutics for prostate cancer. Background topics relating to DC based immunotherapy theory and practice are also addressed. DCs have been recognized as the most efficient antigen presenting cells that have the capacity to initiate naive T cell response in vitro and in vivo. During their differentiation and maturation pathways, dendritic cells can efficiently capture, process and present antigens for T cell activation. These characteristics make DC an attractive choice as the cellular adjuvant for cancer vaccines. Advances in DC generation, loading, and maturation methodologies have made it possible to generate clinical grade vaccines for various human trials. More than 100 DC vaccine trials, including 7 studies of patients with advanced prostate cancer have been reported to date. These vaccines were generally well tolerated with no significant adverse toxicity reported. Clinical responders have been identified in these studies. The new prospects opened by DC based vaccines for prostate cancer are fascinating. When compared to conventional treatments, DC vaccinations have few side effects. Improvements in patient selection, vaccine delivery strategies, immune monitoring and vaccine manufacturing will be crucial in moving DC based prostate cancer vaccines closer to the clinics.

A Mixed-Mode Polynomial Cellular Array Processor Hardware Realization

A mixed-mode cellular array processor is presented in which the processing units (PUs) are coupled with programmable polynomial (linear, quadratic, and cubic) first neighborhood feedback terms. It combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks whereas the integrator is digital, and analog-to-digital and digital-to-analog converters are used to interface between them. A 10-mm/sup 2/, 1.027 million transistor cellular array processor with 2/spl times/72 PUs and 36 layers of memory in each was manufactured using a 0.25-/spl mu/m digital CMOS process. The array processor can perform gray scale Heun's integration of spatial convolutions with linear, quadratic, and cubic activation functions for a 72/spl times/72 data while keeping all input-output operations during processing local. One complete Heun's iteration round takes 166.4 /spl mu/s and the power consumption during processing is 192 mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown.

VLSI efficient discrete-time cellular neural network processor

Typical VLSI implementations of discrete-time cellular neural networks (DTCNN) incorporate costly hardware to implement the basic DTCNN cell, resulting in a small grid size that needs to be cascaded with many other chips for processing images of any practical size. In the paper, a low-cost DTCNN cell that can be incorporated into a single chip in large numbers has been proposed. Memory bandwidth considerations show that 256 DTCNN cells can be incorporated into a single chip DTCNN processor to compute a 256 /spl times/ 256 image at 30 frames per second. Techniques based on rectangular-shaped cell grids for use with video memory have been proposed to satisfy the memory bandwidth requirements. The architecture of the proposed DTCNN processor is also capable of supporting the flexible grouping of basic cells. In addition, the processor, which is capable of supporting the flexible grouping of cells, can be cascaded in a highly scalable manner to facilitate the processing of larger images at high speed.

Demonstration and architectural analysis of complementary metal-oxide semiconductor/multiple-quantum-well smart-pixel array cellular logic processors for single-instruction multiple-data parallel-pipeline processing

We present an optoelectronic-VLSI system that integrates complementary metal-oxide semiconductor/multiple-quantum-well smart pixels for high-throughput computation and signal processing. The system uses 5 x 10 cellular smart-pixel arrays with intrachip electrical mesh interconnections and interchip optical point-to-point interconnections. Each smart pixel is a fine grain microprocessor that executes binary image algebra instructions. There is one dual-rail optical modulator output and one dual-rail optical detector input in each pixel. These optical input-output arrays provide chip-to-chip optical interconnects. Cascading these smart-pixel array chips permits direct transfer of two-dimensional data or images in parallel. We present laboratory demonstrations of the system for digital image edge detection and digital video motion estimation. We also analyze the performance of the system compared with that of conventional single-instruction-multiple-data processors.

Monocyte-derived dendritic cells: development of a cellular processor for clinical applications

Since dendritic cells (DCs) are the most professional antigen-presenting cells, (Schuler et al., 1997), increasing interest in their use in clinical approaches has been observed. (Nestle et al., 1998; Murphy G. et al., 1996). We have developed an ex vivo standardized process for the generation of dendritic-like cells (MAC-DCs) from human blood circulating monocytes. Human monocytes can differentiate into very different functional cells according to the conditions of culture, media and cytokines used. In the present study, we demonstrate that both pure monocytes and mononuclear cells differentiate into DCs when they are grown in defined medium AIM-V in the presence of granulocyte-macrophage colony-stimulating factor (GM-CSF) plus IL13 and in approved biocompatible non-adherent bags. Quality and functional controls of the immature DCs obtained rely on bacterial sterility, viability, morphology and recovery. The MAC-DCs also present an immature DC phenotype with a low expression of CD14 and CD64, and high expression of MHC-I, MHC-II and CD40. They also express B7 costimulatory molecules (CD80, CD86), CD83, and CD1a molecules. They induce strong allogenic T-cell proliferation (mixed lymphocyte reaction as well as proliferation of autologous memory T lymphocytes when incubated in the presence of recall antigens (tuberculosis, Candida albicans, and tetanus toxoid). They also show an increase in phagocytic uptake of yeast, tumour cells and debris. The global closed system which, under reproducible good medical practice (GMP) conditions, enables the production of dendritic cells of clinical quality, has been optimized ("Vac Cell Processor"). It contains all bags, connections, media, reagents, washing solutions, control antibodies, standard operating procedures, data management, traceability and help in the form of dedicated software.

Architecture and Design of 1-D Enhanced Cellular NeuralNetwork Processors for Signal Detection

One-dimensional cellular array processor architecture and design for neural-based partial response (PR) signal detection are presented. Analog parallel computing approaches have many attractive advantages in achieving low power, low cost, and faster processing speed by its uniquely coupled parallel and distributed processing nature. In this paper, we describe the maximum likelihood sequence estimation (MLSE) algorithm for PR signals, the enhanced Cellular Neural Network (CNN) processor array architecture to realize the detection algorithm, and system performance evaluation. Analytical models and simulations on a design example of the detector have been employed to demonstrate the advantages of this scalable VLSI architecture. A processing rate of 265 Mbps was achieved for a prototype detector on a silicon area of 5.14 mm by 5.81 mm is a 1.2 µm CMOS technology. The processing rate can be beyond 1Gbps if it is implemented in the same amount of silicon area by using 0.5 µm CMOS technology. Such promising results clearly demonstrate the ability to meet the needs in future high speed data communication by VLSI realization of maximum likelihood sequence detectors based on the enhanced cellular neural network paradigm.

Image morphological operations and edge detection using optical programmable logic neural networks

Based on the concept of 2-D programmable logic neural networks, an optical programmable image processor for neighborhood operations is proposed. The spatial polarization encoding and space-variant techniques are used in the design of an optical system which can perform multiple-instruction multiple-data image processing. The system is a cellular logic image processor with nine local neighbor inputs and three outputs. In particular, the applications of the optical scheme in binary image morphological operations and edge detection are described in detail. Simulation results are also presented.

Behavioral simulation of densely-connected analog cellular array processors for high-performance computing

The analog cellular neural network (CNN) model is a powerful parallel processing paradigm in solving many scientific and engineering problems. The network consists of densely-connected analog computing cells. Various applications can be accomplished by changing the local interconnection strengths, which are also called coefficient templates. The behavioral simulator could help designers not only gain insight on the system operations, but also optimize the hardware-software co-design characteristics. An unique feature of this simulator is the hardware annealing capability which provides an efficient method of finding globally optimal solutions. This paper first gives an overview of the cellular network paradigm, and then discusses the nonlinear integration techniques and related partition issues, previous work on the simulator and our own simulation environment. Selective simulation results are also presented at the end.