Cellular Processor Research Articles

Solid state integrated optical cellular two-layer logic image processor: design and demonstration

An all solid state integrated optical cellular two-layer logic image processor, which can be used for binary image processing, has been designed and fabricated. The first layer is an optical parallel self-programming logic processor, constructed with prism combinations. The second layer is an optical, morphological dilation processor assembled with birefringent plates. The complete system uses the direct cascade of these two processors. It is shown that the integrated system is compact in structure, insensitive to environmental influences, and efficient in performance.

Gray-tone image processing by threshold superposition in an optical cellular-logic binary-image processor

A parallel architecture for gray-tone image processing is proposed that utilizes the concept of threshold sum-superposition into a cellular two-layer logic binary-image processor. Various processing functions constituted by gray-tone dilation, erosion, fuzzy-logic operations, and arithmetic operations are obtained. The optoelectronic implementation is illustrated.

One-operation image algebra and optoelectronic cellular two-layer logic array

A parallel binary image algebra with a logic operation followed by a dilation is developed in this paper. A cellular two-layer logic image processor architecture is proposed to execute such a one-operation image algebra, which consists of a parallel logic layer followed by a morphological layer. All the possible image processing functions can be written by the algebra. We construct an optoelectronic array based on optical logic operation using spatial coding techniques, optical neighborhood interconnection in a defocused system, and electronic thresholding and feedback. Any image transformation can be performed through iterative programming of the logic operations. Experimental results are also given.

Method and apparatus for recognizing unknown spoken words and by feature extraction and comparison with reference words

Speech recognition is performed in several successive phases, with each word being separated into elements of equal length. Each element is represented by a vector consisting of eight coefficients. After the end of a word is recognized, the word is successively compared with all reference words in a speech recognition apparatus. The recognition process is speeded up through the utilization of common hardware for all phases and by avoidance of idle time. A cellular array processor is used whose processing elements operated predominantly as filters in the feature extraction phase, and each element compares two vectors in the comparison phase. By gradual transitions between ends and beginnings of words, the capacities of all processors are equally utilized. The exchange of data is practically limited to an exchange between adjacent processors and is thus very efficient.

Parallel architectures for digital optical cellular image processing

A parallel digital optical cellular image processor (DOCIP) functionally comprises an array of identical I-bit processing elements or cells, a fixed interconnection network, and a control unit. Four interconnection network topologies are described, and include two variants of a mesh-connected array and two variants of a cellular hypercube network. The instruction sets of these single-instruction multiple-data (SIMD) machines are based on a mathematical morphological theory, binary image algebra (BIA), which provide an inherently parallel programming structure for their control. Physically, a DOCIP architecture uses a holographic optical element in a 3D free-space optical system to implement off-chip interconnections, and an optoelectronic spatial light modulator to implement a 2D array of nonlinear processing elements and (optionally) local on-chip interconnections. Two examples are given. The first, an experimental implementation of a single 54-gate cell of the DOCIP, uses an optically recorded hologram for within-cell optical interconnections, and a spatial light modulator for a 2D array of optically accessible gates. The second, a design for an efficient and more manufacturable architecture, uses a computer-generated diffractive optical element for cell-to-cell interconnections, and a 20 smart-pixel array of DOCIP cells, each cell having electronic logic and optical input/output.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Robust Cellular Processor for Phase Unwrapping

Abstract A new method for phase unwrapping using a lexicographically updated cellular processor is presented. The method is robust concerning noise induced inconsistencies and those caused by invalid data regions. For a phase map containing small noise, the convergence time of the algorithm is only one iteration. When a large number of inconsistencies are present, the proposed technique may typically take 30 to 60 whole field iterations to converge. The number of iterations required increases with the amount of inconsistencies in the wrapped phase map.

Cellular logic bus arbitration

The functional and VLSI design of a novel one-of-N bus arbitration circuit for a time-shared bus-interconnected multiprocessor system is presented. The proposed system is a multilevel, hierarchical, two-bit cellular processor structure. The arbitration protocol of rotating priority has been customised to produce a hierarchical, fairness-oriented, rotating-priority protocol that guarantees efficient and deadlock-free time sharing of the bus, with better complexity measures compared to both rotating- and unequal-priority protocols.

Two-input programmable optical processing units

Descriptions of several two-input programmable Boolean optical processing units are presented. These units were designed specifically for use within the optical cellular logic image processor architecture. Results from an experimental implementation of one of these processors are given. Expansion upon one of these units to produce a serial full-adder and subtractor circuit is also shown to be possible.

The 3-D Computer

The 3-D Computer is an implementation of a cellular array processor. Two technologies which make possible massive numbers of communication channels both between silicon wafers and through them have been developed. A parallel processor (single-instruction-multiple-data stream cellular array processor) has been designed and built to demonstrate the potential of this technological approach. While the 3-D computer which has been built and operated is a small-scale implementation relative to the long-term aims of this technology, it is nevertheless an extremely powerful computer. The current feasibility demonstration 3-D Computer is a 32*32 array of processors partitioned over five wafers stacked one on top of another. The throughput of this machine is >600 million operations per second with a 10-MHz clock, while the projected throughput of a full-scale machine is >100 billion operations per second, again with a 10-MHz clock. >

HCL: A language for low-level image analysis

Pyramids have received a great deal of interest as a data structure for use in hierarchical computer vision. This paper describes a language for the description of pyramid algorithms, supporting conceptually parallel pattern-matching and arithmetic operations. The language is defined by adding constructs from a notation for pyramid algorithms called Hierarchical Cellular Logic to the general-purpose programming language C. Initially developed to support vision research on PCLIP II, a cellular processor with a pyramidal interconnection topology, the language is also implementable on a wide range of parallel architectures.

Cellular array processor CAP and applications

The general-purpose, highly parallel, cellular array processor (CAP) we developed features multiple-instruction stream, multiple-data stream (MIMD) processing and image display. Processor elements can number in several hundreds. The present system uses 256 processors. Each processor element consists of a general-purpose microprocessor, memory, and a special VLSI chip that performs parallel-processing-specific functions such as processor communication and synchronization. The VLSI has two 2M byte/s independent common bus interfaces for data broadcating and six 15M bit/s serial communication ports for local data communication. The chip also can process image data in real time for multiple processors. Use of the communication interfaces enables a variety of processor networks to be configured. One CAP application has been computer graphics, in which ray tracing is used to generate quality images.

Synchronization of asynchronous concurrent processes using cellular automata

The use of a cellular processors network to synchronize a system of asynchronous concurrent processes in a trully parallel manner is demonstrated. The associated problems of deadlock and indefinite postponement are considered with particular reference to the classical synchronization problem known as the Dining Philosophers problem. A hardware model for the solution of the problem is presented. A more practical example such as the use of cellular processors for the synchronization of a multiprocessor system is also considered.

Optical cellular processor architecture 2: Illustration and system considerations

In the first paper of this series, we proposed a definition for the concept of 2-D optical cellular processors. In this second part we present an optical experimental setup capable of implementing a binary pattern recognizer. A 2-D hologram array is used in conjunction with a multiplexed holographic illumination for the interconnection and makes the system easily programmable. Thick phase holograms on dichromated gelatin cause distortion and their field of view is constrained by the Bragg effect. These problems are investigated in relation to all the system aberrations and a set of optimal parameters for one distortion-free configuration is given. Experimental results are shown.

Binary image algebra and optical cellular logic processor design

Binary image algebra and optical cellular logic processor design

Megacell machine

A general purpose highly parallel cellular processor, called Megacell Machine, has been studied and developed. This paper presents the architecture of the Megacell Machine, discusses the possibilities of LSI, VLSI, WSI implementation, sketches its programming methodology and programming languages. Some application fields (image processing, matrix operations, finite-element analysis, etc.) and performance data will be mentioned.

Optical cellular processor architecture 1 : Principles

General characteristics and advantages of 2-D optical cellular processors are listed and discussed, with reference to the concepts of cellular automata, symbolic substitution, and neural nets. The role of optical interconnections and of quasilinear processing combining linear array operations and pointwise nonlinearities is highlighted. An architecture for optical implementation of cellular automata is introduced; it features high density 3-D optical shift-invariant interconnections and programmability of the interconnection pattern through adequate use of holographic connectors.

Optical generation of random-number arrays for on-chip massively parallel Monte Carlo cellular processors

Stochastic optical phenomena can be used for generation of random-bit arrays with a prescribed probability law that may vary in space and in time. This is useful for implementation of Monte Carlo algorithms, including simulated annealing, with a high recursion rate by monolithic massively parallel arrays of processing elements. Each processing element includes a photosensor. The use and advantages of speckle and of microchannel-plate image intensifiers amplifying single-photon events are considered.

ALTEP — A cellular processor for high-speed pattern matching

The design of a high-speed cellular pattern matcher, called theAssociative Linear Text Processor (ALTEP), is presented.ALTEP was originally designed for systems which use signature files as an access method. However, it is also suitable for systems which store the database in fixed length blocks.ALTEP is a linear array of logic cells which respond to commands sent from a central controller over a bus. A text block is loaded into the cells and pattern characters are broadcast to the cells for comparison.ALTEP has the capability of recognizing full regular expressions and is the only cellular logic array which has this capability. It requiresO(p) steps for patterns which do not contain closures andO(len(max(T(P)))) steps for closures, wherep is the the length of the pattern andlen(max(T(P))) is the length of the longest substring in the text which matched the closure.

Implementation of a Prototype Cellular Logic Array Processor

A prototype cellular logic array processor (CLAP-4), which has been indigenously constructed using TTL integrated circuits, can process 8 by 4 arrays of 4-bit image data in parallel, i.e. simultaneously, as a consequence of the parallel architecture which enables acceptance of contextual information from the neighbourhood of a pixel. Further CLAP-4 provides 48 arithmetic/logical operations on (up to) three operand images. In this paper, a description of the structure of CLAP-4 is presented.

Some results of speech analysis by parallel processor

Commercially available parallel processors with special cellular computer architecture are able to perform certain nonlinear transformations, viz., the covering transformations much more efficiently than Von Neumann type machines. Additionally, these computers' interactive image processing capabilities often result in discovering insightful ways of approaching old problems. It is natural to inquire whether the inherent advantages of cellular processors would be of benefit in speech analysis. This paper discusses the early results obtained by treating the speech spectrogram as an “image” and analyzing this “image” on a Cytocomputer™. Results include the characterization of the distinctive features of speech in mathematical morphological terms. Examples of morphological transformations of speech spectrograms will be presented which suggest applications in speech analysis, automatic speech recognition, speech synthesis, bandwidth compression, and speech enhancement.