Cell Layout Research Articles

Incorporating cell hierarchy to decipher the functional diversity of single cells.

Cells possess functional diversity hierarchically. However, most single-cell analyses neglect the nested structures while detecting and visualizing the functional diversity. Here, we incorporate cell hierarchy to study functional diversity at subpopulation, club (i.e., sub-subpopulation), and cell layers. Accordingly, we implement a package, SEAT, to construct cell hierarchies utilizing structure entropy by minimizing the global uncertainty in cell-cell graphs. With cell hierarchies, SEAT deciphers functional diversity in 36 datasets covering scRNA, scDNA, scATAC,and scRNA-scATAC multiome. First, SEAT finds optimal cell subpopulations with high clustering accuracy. It identifies cell types or fates from omics profiles and boosts accuracy from 0.34 to 1. Second, SEAT detects insightful functional diversity among cell clubs. The hierarchy of breast cancer cells reveals that the specific tumor cell club drives AREG-EGFT signaling. We identify a dense co-accessibility network of cis-regulatory elements specified by one cell club in GM12878. Third, the cell order from the hierarchy infers periodic pseudo-time of cells, improving accuracy from 0.79 to 0.89. Moreover, we incorporate cell hierarchy layers as prior knowledge to refine nonlinear dimension reduction, enabling us to visualize hierarchical cell layouts in low-dimensional space.

Forked-contact and dynamically-doped nanosheets to enhance Si and 2D-material devices at the limit of scaling

We propose a novel Forked-Contact, Dynamically-Doped Multigate transistor as ultimate scaling booster for both Si and 2D materials in aggressively-scaled nanosheet devices. Using accurate dissipative DFT-NEGF atomistic-simulation fundamentals and cell layout extrinsics, we demonstrate superior and optimal device characteristics and invertor energy – delays down to sub-30-nm pitches, i.e., a 10 nm scaling boost compared to the nanosheet MOSFET references, regardless of the material system used. This gain is linked to a more compact architecture but does not change the material-specific fundamental gate-length limit that we also assess here. By switching from Si to 2D materials, however, an additional 5 nm reduction in gate length scaling could be enabled.

EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation

This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;5\times $ </tex-math></inline-formula> reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. Furthermore, exploiting the magneto-quasistatic (MQS) regime of operation of the EM leakage from the CMOS circuits, the HFSS-based framework is utilized to develop a pre-silicon (Si) EM SCA evaluation technique to assess the vulnerability of cryptographic implementations against such attacks during the design phase itself.

Scheduling of Multi-Robot Job Shop Systems in Dynamic Environments: Mixed-Integer Linear Programming and Constraint Programming Approaches

This paper investigates a dynamic scheduling problem within a job shop robotic cell, wherein multiple robotic arms are responsible for material handling in a U-shaped arrangement. Each robotic arm has access to specific workstations based on their distance in the cell layout. Therefore, a part may need to be exchanged between several robots according to its process plan. For this purpose, intermediate buffers are positioned between each pair of consecutive robots. Due to the dynamic nature of the problem, new jobs arrive at unpredictable times, which in turn necessitates rescheduling taking the system’s current state into account. To tackle this problem, firstly, a Mixed-Integer Linear Programming (MILP) model is devised. Secondly, three distinct Speed-up Constraints (SCs) derived from the problem’s inherent characteristics are designed and implemented to accelerate the MILP model’s solving procedure. Afterward, the problem is formulated using Constraint Programming (CP) approach. The performance of the CP model and the MILP model in presence of all possible combinations of the SCs are evaluated and compared through solving various random instances. Next, an analysis is performed on the buffers’ pick-up criterion and how it is affected by the problem’s size. Besides, the impact of changes in the robots’ speed on the productivity of the cell is assessed. Finally, the extent to which the rescheduling priority affects the output of the model is studied.

Manufacturing Cell Integrated Layout Method Based on RNS-FOA Algorithm in Smart Factory

The research on the layout of multi-layer manufacturing cells for smart factories is still in its infancy, but there is an urgent need to address this issue in building smart factories. This paper presents the Manufacturing Cell Integrated Layout (MCIL) Method, which integrates multiple layout forms of multi-layer and single-layer manufacturing cells. The paper develops a mathematical model of the MCIL problem which considers the multi-objective functions of logistics handling, occupied space, cell stability, lost time, and non-logistics relations, as well as the constraints between equipment in the cell and cells. An adaptive RNS-FOA algorithm is proposed to solve the high-dimensional and large-scale characteristics of the MCIL problem based on the research of academics. Lastly, a case demonstrates the outstanding contribution of the mathematical model to the solution of the MCIL problem, while simultaneously validating the efficiency and stability of the RNS-FOA algorithm for solving the MCIL problem.

A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules

Design rule (DR) is the most critical challenge for generating a cell layout automatically in the advanced process technologies (e.g., finFET-EUV). Previous works explicitly encode the complicated DRs into routing constraints and automation scripts, which may not be general and efficient for addressing the DR problem. Therefore, an automatic cell layout generation (ACLG) framework is proposed and adopts three implicit-learning techniques [i.e., guidance learning (EGL), DR learning (DRL), and mistake-driven learning (MDL)], which jointly discover the knowledge of complex DRs from the existing layouts in the cell library. EGL learns the geometry behavior of the target metals from the legal cell layouts. DRL learns the DRs from layout patterns. MDL learns the routing constraints iteratively from the encountered mistakes during the layout generation (LG). These three implicit-learning techniques are combined into ACLG and developed into four core stages to cope with the DR challenge in a more general and efficient way. The experimental results demonstrate that ACLG effectively solves all the DR violations (DRVs) in an advanced finFET-EUV process (100% success rate on fixing DRVs) and successfully yields DRC-clean cell layouts for 13 benchmark cells. In addition, the proposed DRL technique is more efficient than the commercial DRC tool in excluding the illegal layout solution space. The number of iterations for a generated legal cell layout is reduced by 30% on average with DRL (3.31) compared to the commercial DRC tool (4.69). Moreover, the total runtime of generating legal layouts for 13 benchmark cells is further improved by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.57\times $ </tex-math></inline-formula> on average. Since DRL not only reduces the iterations of refining the DRVs in the generated cells but also speedups the process of DR checking (DRC) efficiently.

Electrochemical Impedance Spectroscopy as an Analytical Tool for the Prediction of the Dynamic Charge Acceptance of Lead-Acid Batteries

The subject of this study is test cells extracted from industrially manufactured automotive batteries. Each test cell either had a full set of plates or a reduced, negative-limited set of plates. With these test cells the predictability of the dynamic charge acceptance (DCA) by using electrochemical impedance spectroscopy (EIS) is investigated. Thereby, the DCA was performed according to EN 50342-6:2015 standard. The micro cycling approach was used for the EIS measurements to disregard any influencing factors from previous usage. During the evaluation, Kramers-Kronig (K-K) was used to avoid systematic errors caused by violations of the stationarity, time-invariance or linearity. Furthermore, the analysis of the distribution of relaxation times (DRT) was used to identify a usable equivalent circuit model (ECM) and starting values for the parameter prediction. For all cell types and layouts, the resistance R1, the parameter indicating the size of the first/high-frequency semicircle, is smaller for cells with higher DCA. According to the literature, this semicircle represents the charge transfer reaction, thus confirming that current-enhancing additives may decrease the pore diameter of the negative electrode.

Thermal Design of VCSEL Arrays for Optical Output Power Improvement

This study investigates the thermal design of 2-D vertical-cavity surface-emitting laser (VCSEL) arrays for optical output power improvement. Considering the temperature dependencies of bias current, internal quantum efficiency, internal optical loss, and thermal resistance of each array cell, a compact electro-opto-thermal model of 2-D VCSEL arrays with linear power dissipation and quadratic power dissipation in each array cell is established to study the effects of array cell spacing and layout on the device performance. At the same time, the power dissipation mechanisms contributing to thermal rollover are also studied. It is found that the array cell spacing has a strong influence on the linear power dissipation, and the layout (such as hexagonal design) influences quadratic power dissipation obviously. With the careful design of array cell spacing and layout, both the temperature profile and the thermal resistance matrix of VCSEL arrays are improved, which is helpful to delay the onset of thermal rollover and hence enhance the optical output power. The simulation results are consistent with experimental results.

Optimal design of shape changing mechanical metamaterials at finite strains

Programmable metamaterials establish a new subset of metamaterials offering controllable and variable physical properties. As metamaterials, they are artificial materials and exhibit exotic and counter-intuitive material behavior, but are more specifically tailored for engineering purposes. Whereas for metamaterials a mostly homogeneous layout of unit cells is considered, programmable materials are constructed by an individual distribution in order to satisfy custom intentions regarding a specific shape change under given loading conditions. In order to tackle this customization of material response, a computational optimization framework similar to topology or material optimization is proposed. Our work is based on a multiscale and data approach, allowing a broad range of application with different classes of unit cells and target functions under finite strains. In this contribution, we present the complete process chain from a parametrized unit cell to the final model of the programmable material, ready to be manufactured. We show numerical results with different unit cells and compare them to fully resolved simulations. Further, with the development of new generative manufacturing processes, the production of such programmable materials consisting of spatially varying cells has also become possible on an industrial scale. One example of lab-scale production is shown in the paper and compared to simulation results.

Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETs with 3D Cellular Layouts

This work presents for the first time a comparative numerical study on the performance of planar 3.3 kV SiC MOSFETs during clamped and unclamped inductive switching for various cell layouts and pitches. It is demonstrated that despite its larger on-state losses, the atomic lattice layout (ALL) incurs smaller switching losses than the stripe and the circular designs for all examined cell pitches. Conversely, while the ALL does turn off earlier than the other layouts during UIS, the decrease in the peak lattice temperature that it brings is predicted to be marginal if just a single unit cell is considered.

On the Short Circuit Electro-Thermal Failure of 1.2 kV 4H-SiC MOSFETs with 3D Cell Layouts

In this manuscript, the short circuit (SC) capability of 1.2 kV vertical double diffused SiC MOSFET with different layout topologies is investigated. 3D finite element electro-thermal simulations have been carried out in order to assess the performance of five different cell topologies. It has been found that while the maximum drain current density observed during a SC event agrees well with the specific on-state resistance behaviour, the maximum temperature evolution in the unit cell follows the opposite trend. This behaviour can be explained by the relatively poor spreading of the carriers in the JFET region (of the ALL) at small cell pitches (~ 8um), which can lead to the formation of a filament with a high current density and heat generation.

Exact approaches for the combined cell layout problem

We consider the Combined Cell Layout Problem (CCLP) as well as the Multi-Bay Facility Layout Problem (MBFLP) and Layouts with Pier-Type Patterns, which are both special cases of the CCLP. Given a number of cells of type single-row or directed circular, pairwise distances between the cells and a set of one-dimensional departments with pairwise transport weights between them, the CCLP asks for an assignment of the departments to the cells such that departments in the same cell do not overlap and such that the sum of the weighted center-to-center distances is minimized. Distances between departments in the same cell are measured according to the layout type of the cell and otherwise their distance equals the sum of the distances to the associated (un)loading positions of the cells plus the distance between the cells. The CCLP and its variations have wide applications. Nevertheless approaches for solving the CCLP exactly have not been presented in the literature before. We solve the CCLP exactly by enumerating over all assignments of the departments to the cells and solving several CCLP with fixed-cell assignment. We show how to reduce the number of distinguishable cell assignments significantly by merging two cells of type single-row. This leads to a new well-performing exact approach for the CCLP where arising subproblems are solved via (new) mixed-integer linear programming models. In a computational study we compare the computation times and the optimal values of various facility layout problems in order to support the decision maker to choose a layout.

Metasurface absorber with ultra-thin thickness designed for a terahertz focal plane array detector.

Terahertz (THz) refers to electromagnetic waves with frequency from 0.1 to 10 THz, which lies between millimeter waves and infrared light. This paper proposes an ultra-thin metasurface absorber which is perfectly suited to be the signal coupling part of terahertz focal plane array (FPA) detector. The absorptance of the proposed metasurface is higher than 80% from 4.46 to 5.76 THz (25.4%) while the thickness is merely 1.12 µm (0.018 λ). Since the metasurface absorber will be applied to terahertz FPA detector which requires planar array formation, it is divided into meta-atoms. Each meta-atom consists of the same unit cell layout, and air gaps are introduced between adjacent meta-atoms to enhance the thermal isolation, which is crucial for FPA detector to obtain desired imaging results. Due to the symmetrical layout of meta-atoms, absorptance keeps stable for different polarized waves, moreover, good absorptance could also be achieved for incidence angles range of ± 30 °. Spectral measurements show good agreement with the simulation. As a result, features of ultra-thin thickness, polarization insensitivity, and high absorptance make the proposed metasurface absorber well suited to highly efficient coupling of terahertz signals in FPA detector.

Grouping Maching using Genetic Algorithm for Dynamic Cell Layout Design

Changes in the manufacturing sector due to changes in shorter product life cycles, market demands and also use of the latest technology in the company, this will result in changes in process flow and also change the layout in the production section, causing dynamic layout problems. Dynamic layout problems can be solved by using a manufacturing cell formation method which has a high degree of flexibility. In this study, algorithms used for grouping machines into manufacturing cells are Direct Clustering Algorithm and Rank Order Clustering. Then it will be improved by using Genetic Algorithm. The Dynamic Modified Spanning Tree Algorithm is also used to sort machines into a layout with a single-row structure and determine the length of the planning time window in the future. The goals of this research is to get the best solution from the two methods of grouping machines/parts into manufacturing cells and to obtain improvement results using Genetic Algorithms. For the design industry, the resulting dynamic cell layout is expected to reduce production costs, save material handling, be efficient in material flow, which in turn will be able to compete globally.

A Review on Advances in Electrocatalytic N2 Reduction to Ammonia

Ammonia is one of the most important industrial chemicals which is prepared by the traditional Haber–Bosch process. Haber–Bosch process is an expensive process requiring higher temperature, pressure, and a lot of energy. Electrocatalytic nitrogen reduction reactions (NRR) have gained a lot of interest as the alternate method for the production of ammonia. For obtaining a higher yield, higher Faradic efficiency (PE), inhibition of side reactions e.g., hydrogen evolution reaction (HER), and reducing the production cost for ammonia by NRR, selection of appropriate catalysts, cell layout, and electrolyte selection are important controlling parameters for the NRR. Non-metallic catalysts are preferred over noble metallic catalysts due to their lower cost, more resources, and characteristic dorbital electron but have the issue of low selectivity due to the higher HER. The selectivity for the NRR can be improved by employing the catalysts with higher absorption of N2. PEM-type cells and the back-to-back cells are used to inhibit the HER. Apart from these factors, NRR is also dependent on other factors to obtain better experimental results e.g., no nitrides, removing the ammonia from contaminants sites, and controlling the experiment time.

Temperature Dependence of 55 nm Gate Oxide, 2.3 kV SiC Power JBSFETs With Linear, Hexagonal, and Octagonal Cell Layouts

The electrical characteristics of 2.3-kV 4H-SiC power Junction Barrier Schottky Field-Effect Transistors (JBSFETs) fabricated with 55-nm gate oxide thickness are reported as a function of temperature for the first time. The behavior of three cell topologies (linear, hexagonal, and octagonal) is compared. Excellent JBSFET characteristics are demonstrated up to 150 °C. The ON-resistance was found to increase by 45% from 25 °C to 150 °C for the linear and hexagonal cell layouts, which is much less than the 100% increase previously reported for silicon carbide (SiC) power MOSFETs. The threshold voltage decreases with temperature but remains above 1.2 V even at 150 °C for all cases. The third-quadrant current flow via the integrated JBS diode is confirmed to suppress body diode conduction at all temperatures. The leakage current remains below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1~\mu \text{A}$ </tex-math></inline-formula> even at 150 °C despite the presence of the Schottky contact in the JBSFET structure due to optimum JBS diode design. The octagonal cell topology is shown to exhibit the best figures of merit (FOMs) FOM[ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{C}_{ \mathrm{\scriptscriptstyle GD}}$ </tex-math></inline-formula> ] and FOM[ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{ Q}_{ \mathrm{\scriptscriptstyle GD}}$ </tex-math></inline-formula> ] even at elevated temperatures. The observed device behavior is explained using device analytical modeling. The analytical modeling reveals that the reduced rate of increase in ON-resistance with temperature for the 2.3-kV SiC JBSFETs is due to the relatively large source contact resistance produced by the lower (900 °C) contact anneal temperature. The lower anneal temperature is required to simultaneously make the Schottky contact for the JBS diode.

Selective Staining on Non-Volatile Memory Cells for Data Retrieval

A new data retrieval approach utilizing selective staining is explored to differentiate “0” from “1” cells in EEPROM and Flash memory cells with node size of 40 nm and 250 nm. A two-step staining process based on selective oxide etching and copper galvanic displacement deposition is introduced. The underlying mechanism is attributed to the difference in electric field across the tunnel oxide, which originates from the presence or absence of charges stored in the floating gates. With proper sample preparation, the selectively stained and non-stained cells can be characterized with optical microscopy and scanning electron microscopy, to facilitate direct read-out of data in a time-efficient manner. The physical layout of individual memory cells with respect to the stored data is identified. A systematic data retrieval is achieved with an accuracy of 95% at individual bit level. This selective staining technique marks the data permanently on the chip that allows for subsequent analysis and evidence retention.

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform

Innovative robotization of manual manufacturing processes

Manufacturing industries are continually challenged to adapt to a competitive environment. Consequently, there is an urgency to opt for automation technologies to upgrade their manufacturing facilities and make them more flexible. Especially this relates to automating manual manufacturing processes, which is often challenging to structure to ensure repetitiveness and generalization to other processes within the facility. Consequently, innovating systematic approaches to identify robotization opportunities is an interesting proposition for manufacturing set-ups that would like to integrate collaborative robots on the shop floor and struggle with the decision steps to follow.In this paper, a framework for supporting robotization effort for manufacturing set-ups is proposed. The methodology consisting of five phases, culminating in the identification of robotization opportunities. A case for manual milling manufacturing processes is demonstrated as a ‘proof-of-concept’. The first step of the proposed approach focuses on task decomposition, in which manual manufacturing tasks are characterized. This is followed by task allocation to a robot and human agent based on intrinsic characteristics of the task to capabilities of the agent. Next, alternative layout configurations for candidate cell layouts are generated. In the final step, a candidate layout is selected and modeled in an agent-based simulation platform, considering factors such as realism, interaction safety between the robot and human agent, and interesting manufacturing metrics such as resource utilization and throughput rate. A final configuration is optimized, which visualizes a collaborative robot performs loading and unloading tasks alongside an operator performing highly cognitive tasks. For safety, zoning of the manufacturing cell is visualized, considering a working area separated by a safety fence.

A Novel Mathematical Model for Tillage Production Planning and Facility Layout Design

Cell formation and layout design are important steps in the implementation of production systems. Existing models focus mainly on the problem of cell formation and machine layout design and cell location in a dynamic environment, with the exception of a few recent studies. Also, in many existing articles, binary information has been used for cell formation and other information such as production volume, operation sequence and lower production costs have played a role in the structure of existing models. In this paper, a nonlinear programming model under possible dynamic conditions is presented. The objectives of the model include minimizing the total costs of intracellular and intercellular movements of parts, the existence of exceptional parts, intercellular layout of machines, operating costs, fixed costs of machines and the cost of the difference in demand estimated by the model from its expected value. A genetic algorithm is used to solve and the results are compared with the optimal solution.