Cascode Current Source Research Articles

A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS

This paper proposed a pipelined analog-to-digital converter (ADC) that utilizes a high-linearity input buffer and a two-step input-split fully differential ring amplifier (ringamp). The implemented input buffer based on a gain-boost cascode current source, is optimized for linearity over a wider frequency range by suppressing fluctuations in tail current. To save power consumption without compromising common-mode and power-supply rejection, a fully differential ring amplifier is employed as the residue amplifier. Additionally, a correlation-based calibration is implemented, which involves injecting pseudo-random dither signals into each multiplying digital-to-analog converter (MDAC) stage to enhance linearity. Fabricated in a 28-nm CMOS process, the 1.25-GS/s 10-bit ADC achieves a spurious-free dynamic range (SFDR) of 70.7 dB and a signal-to-noise-and-distortion ratio (SNDR) of 50.3 dB at Nyquist input. The core conversion circuits of the ADC consume only 30.2 mW from a single 1-V supply. This translates to a Walden figure of merit (FoM) of 90 fJ/conversion-step and a Schreier FoM of 153.5 dB, respectively.

An improved memristive current mirror circuit for continuous adjustable current output

The traditional mirror current source circuit has been widely used in analog circuits. However, the output current of this circuit is not adjustable after the circuit is manufactured, which is a difficult issues. To solve this problem, this paper proposes a memristive continuously adjustable cascode current source. In this paper, we introduce two additional MOS transistors and a memristor to the circuit architecture of the cascode current mirror. This modified design achieves electrical isolation between the improved cascode current source and the memristor control circuit. By incorporating a memristor control circuit, we are able to regulate the memristance in the main circuit, which in turn allows for continuously adjustable output current. The mathematical relationship between the control signal and the output current of the memristor control circuit is derived in this paper, and the mathematical model is verified using PSPICE. The simulation results show that the continuously adjustable cascode current source based on the memristor achieves continuous regulation of the output current and high accuracy of the output current. This paper provides a technical solution to the problem that the traditional current source circuit cannot realize the continuous adjustable output current.

Design of 8-Bit Hybrid Current Steering Digital to Analog Converter in a Standard 65nm CMOS Technology

A digital-to-analog converter (DAC) in electronics is a device that transforms digital signals into analog signals. There are various DAC architectures, and DAC's usefulness for a given application is determined by factors like resolution, INL, DNL, power consumption, maximum sampling frequency, and others. Because digital-to-analog conversion may damage a signal, a DAC with negligible faults for the application should be used. The current-steered digital-to-analog converter is well suited for high-speed applications because no buffers are needed for current steering architectures and the output is the total current drawn from the supply. In this paper, an 8-bit hybrid current steering digital-to-analog converter is proposed. Four cascode current sources with different weights are used in this architecture. The UMC 65nm CMOS technology was used to design the digital-to-analog converter. The INL and DNL were +0.19/-0.15 LSB and +0.28/-0.11 LSB respectively. The DAC uses roughly 3.25 mW at a supply voltage of 1.2V and a sample rate of 100 MHz. 12.751 mV was the output voltage at full scale. In comparison to earlier reports, the power, INL, DNL, and chip area used by the digital-to-analog converter in this architecture were significantly lower. It is appropriate for use in portable devices.

Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator

A tiny-size ultra-low voltage CMOS voltage reference operating at quiescent picoamp scale has been proposed in this paper to fit the high standards of modern wireless microsystems. Without any on-chip resistor or operational amplifier (opamp), the sensitive core of the proposed voltage reference is protected from the glitches of the power supply via a temperature-dependent cascode current source biased by the output. The upper limit of the output temperature range is broadened by the increased diode leakage current of the proposed current generator. The case study deals with implementation of the new circuit and post-layout simulation results in 0.18-μm CMOS technology. The circuit occupies an active area of 629 μm2, consuming almost 690 pA from 0.3 V minimum supply voltage at room temperature. The untrimmed 229 mV output voltage exhibits an average temperature coefficient (TC) of 47.39 ppm/°C over the −40 °C–140 °C temperature range. The line-voltage sensitivity (LS) is 0.17%/V when the input supply is varied from 0.3 V to 1.8 V, and can be improved by 9 × if the lower limit of the power supply is increased to 0.4 V. The DC power supply ripple rejection (PSRR) is lower than −80 dB for the line voltage beyond 0.5 V.

Design of a sub-1V CMOS reference voltage generator

In this paper a low complexity, sub-1V, reference voltage generator with low voltage sensitivity over PVT variation and high power supply rejection ratio (PSRR) is proposed. It consists of a traditional bandgap reference core where resistors are used for generating both the PTAT and CTAT currents, which are then added forming a temperature-independent current. A new 1 V modified folded cascode operational amplifier is proposed and used in the main bandgap’s loop resulting in low offset, high loop gain and adequate loop phase margin of 58.9°. The loop consists of only two inverting stages and the circuit can be integrated entirely without the need of external large capacitors for frequency compensation. A regulated cascode current source is employed for accurately mirroring of the core temperature-independent current to a resistive load, where the reference voltage is generated. The proposed circuit was simulated in SPECTRE achieving an output reference voltage variation of 3.62%, without trimming, over process variation corners with ±10% variation of the 1 V power supply voltage and within the industrial temperature range, from −40 °C to 125 °C. The temperature coefficient from −40 °C to 125 °C is 6.81 ppm/°C at 1 V at the typical process corner. The PSRR at 1 Hz and the output RMS noise within a bandwidth of 100 MHz are −69.85 dB and 279 μV RMS, respectively, at the typical process corner, at a supply voltage of 1 V and temperature of 27 °C. Typical power consumption is 452 μA at 1 V.

A 6.3 GHz high bandwidth voltage-to-time converter with high linearity

A voltage-to-time converter (VTC) architecture with high-bandwidth SFDR performance is presented. This VTC circuit is compatible with high-speed, high-bandwidth RF ADC systems. The proposed VTC utilizes the bottom plate sampling of the capacitor. A constant current source charges the capacitor and generates a ramp signal, which passes through the threshold comparator to output the time pulse signal. An independent sampling process RC loop is adopted to improve the input bandwidth of VTC. The circuit architecture of the cascode current source charging directly to the capacitor provides the linearity of the VTC. A novel bootstrapped switch is employed to further improve the linearity of VTC. The prototype VTC was fabricated in a 65 nm CMOS process with an active area of 0.008 mm2. It exhibits an SNR of 62.7 dB and an SFDR of 54.6 dB for an input frequency of 6 GHz and a sampling rate of 500 MS/s under the TT process corner simulation.

A Low Noise Amplifier Suitable for Biomedical Recording Analog Front-End in 65nm CMOS Technology

This paper presents a fully integrated front-end, low noise amplifier (LNA), dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input-referred noise of the LNA, without adding any additional power. The proposed technique implemented in 65[Formula: see text]nm CMOS technology achieves 30 dB closed-loop voltage gain, 0.05[Formula: see text]Hz lower cut-off frequency and 100 MHz 3-dB bandwidth. It operates at 1.2[Formula: see text]V power supply and draws 1[Formula: see text][Formula: see text]A static current. The prototype described in this paper occupies 3300[Formula: see text][Formula: see text]m2 silicon area.

A 0.13-<inline-formula> <tex-math notation="LaTeX">$\mu\text{m}$ </tex-math> </inline-formula> CMOS SoC for Simultaneous Multichannel Optogenetics and Neural Recording

This paper presents a 0.13- $\mu \text{m}$ CMOS system-on-chip (SoC) for simultaneous multichannel optogenetics and multichannel neural recording in freely moving laboratory animals. This fully integrated system provides 10 multimodal recording channels with analog-to-digital conversion and a four- channel LED driver circuit for optogenetic stimulation. The bio-amplifier design includes a programmable bandwidth (BW) (0.5 Hz–7 kHz) to collect either the action potentials (APs) and/or the local field potentials (LFPs) and has a noise efficiency factor (NEF) of 2.30 for an input-referred noise of 3.2 $\mu V_{\text {rms}}$ within a BW of 10–7 kHz. The low-power delta–sigma ( $\Delta \Sigma $ ) MASH 1-1-1 analog-to-digital converter (ADC) is designed to work at low oversampling ratios (OSRs) (≤50) and has an effective number of bits (ENOB) of 9.75 bits at an OSR of 25 (BW of 10 kHz). The utilization of a $\Delta \Sigma $ ADC is the key to address the flexibility needed to address different noise versus power consumption tradeoff of various experimental settings. It leverages a new technique that reduces its size by subtracting the output of each $\Delta \Sigma $ branch in the digital domain, instead of in the analog domain as done conventionally. The ADC is followed by an on-chip fourth-order cascaded integrator-comb (CIC4) decimation filter (DF). A whole recording channel, including the bio-amplifier, the $\Delta \Sigma $ MASH 1-1-1, and the DF consumes 11.2 $\mu \text{W}$ . Optical stimulation is performed with an LED driver using a regulated cascode current source with feedback that can accommodate a wide range of LED parameters and battery voltages. The SoC is validated in vivo within a wireless experimental platform in both the ventral posteromedial nucleus (VPM) and cerebral motor cortex brain regions of a virally mediated Channelrhodopsin-2 (ChR2) rat.

Beyond Rail-to-Rail Compliant Current Sources for Mismatch-Insensitive Voltage-to-Time Conversion

This brief presents beyond rail-to-rail (BR2R) compliant cascode current sources to markedly improve the compliance voltage and output impedance of the extensively used wide-swing cascode current source. The proposed BR2R sources employ a bootstrapping technique to linearly charge a load capacitor to beyond the supply rails $V_{\mathrm{ dd}}$ or $gnd$ while maintaining an improved output impedance over an equivalent wide-swing cascode source. A process and mismatch-insensitive differential voltage-to-time (DVT) converter employing these BR2R sources is fabricated in 65-nm CMOS and occupies $0.021~\text {mm}^{2}$ , while dissipating $47~\mu \text{W}$ at 1 V. The measured BR2R DVT signal to noise and distortion ratio is 50.2 dB, compared to 38.7 dB for the wide-swing cascode-based DVT within a 2-MHz input bandwidth. The DVT achieves a common mode rejection ratio of 35.1 dB for a 0.4–0.6-V input common-mode range.

A 2-40 Gb/s PAM4/NRZ Dual-mode Wireline Transmitter with 4:1 MUX in 65-nm CMOS

This paper presents a 2-40 Gb/s dual-mode wireline transmitter supporting the four-level pulse amplitude modulation (PAM4) and non-return-to-zero (NRZ) modulation with a multiplexer (MUX)-based two-tap feed-forward equalizer (FFE). An edge-acceleration technique is proposed for the 4:1 MUX to increase the bandwidth. By utilizing a dedicated cascode current source, the output swing can achieve 900 mV with a level deviation of only 0.12% for PAM4. Fabricated in a 65-nm CMOS process, the transmitter consumes 117 mW and 89 mW at 40 Gb/s in PAM4 and NRZ at 1.2 V supply. © 2018, Institute of Electronics Engineers of Korea. All rights reserved.

Ultra‐low power comparator with dynamic offset cancellation for SAR ADC

An ultra-low power dynamic comparator is proposed with low dynamic offset variation for successive approximation register (SAR) analogue-to-digital converter (ADC). Dynamic offset can be cancelled with the cascode current source. Moreover, the power consumption can be reduced because it has no power consumption during the reset phase. With body-driven technology and cross-coupled inverter, the positive feedback during the regeneration is enhanced, which reduces remarkably delay time. Simulation results in a 0.18 μm CMOS technology confirm the performance of the proposed comparator. It is shown that the fluctuation of the total offset voltage (mean + 3std) is 0.15 and 0.39 mV with common-mode voltage from 0.5 V DD to V DD at supply 1.2 and 0.6 V through Monte Carlo simulation, respectively. Furthermore, the delay of the proposed structure can be decreased to 1.837 and 118.2 ns at supply voltages of 1.2 and 0.6 V, while the power consumption is only 18.6 μW and 144 nW, respectively.

Low phase noise LC VCO with sinusoidal tail current shaping using cascode current source

Tail current shaping is a known technique for phase noise reduction. According to this technique, close to outputs zero crossing points, where Impulse Sensitivity Function (ISF) is maximum, current supplying path to the transistor pair is disconnected. In this paper, tail current shaping is performed by two additional transistors that are placed in cascode configuration with the tail current source. Conventional tail current shaping is performed by two tail transistors with the gates connected to the oscillator outputs. The proposed circuit outperforms the conventional circuit in phase noise performance, due to four mechanisms: higher impedance seen from the common source of switching transistors due to cascode current source; better tail current shaping; higher oscillation amplitude with the same power consumption; and lower RMS value of the effective ISF. Also, the proposed circuit presents more stable bias point and output amplitude, compared to conventional circuit. In addition, higher ratio of start-up tail current to the minimum of shaped tail current for the proposed circuit, removes the need for additional start-up detection circuits. Post layout simulations predict a sample oscillator designed at 4GHz in 0.18µm RF CMOS technology presents 11.3 and 3.8dB less phase noise at 1MHz offset, compared to simple and conventional oscillators, respectively.

Fully differential charge-pump comparator-based pipelined ADC in 90 nm CMOS

In this paper, a fully differential charge-pump comparator-based pipelined analog-to-digital converter (ADC) is presented. The fully differential capacitive gain doubler is used in the first stage as multiplying digital-to-analog converter (MDAC). Since the first stage cannot drive large capacitive loads, therefore a topology with high input impedance is chosen for the second, third and following stages. This topology does not require the common-mode feedback (CMFB) circuit. Besides, it employs the cascode current source to minimize the overshoot at the output of stages. The proposed ADC has been designed and simulated in a 90nm CMOS technology. Simulation results show that the ADC achieves SNDR of 55.6dB and SFDR of 64.5dB at sampling frequency of 100MS/s and consumes 2.8mW from a 1V power supply.

Application of cascode level shifter for EMI reduction in LCD driver IC

Purpose – This paper aims to design the circuit for electromagnetic interface (EMI) reduction in liquid crystal display (LCD). Design/methodology/approach – The cascode level shifter and segmented driver circuit are applied in LCD column driver integrated circuit (IC) for EMI reduction. Cascode current mirror is used in the proposed level shifter for DC voltage biasing and reduction of the driving current which passes through the level shifter. The on-off switching currents and transient times are measured and compared between the conventional and proposed level shifters. Additionally, a segmented data latch is obtained by the timing spread solution in data latch, and applied to split the large peak switching current into a number of smaller peak current. The timing spread-operation does not actually reduce the total power of the noise, instead, it spreads the noise power evenly over the frequency bandwidth. The optimal number of latch is dependent on the operating frequency and EMI allowance. The column driver IC and clock controller are integrated in 0.18 μm CMOS technology with 1-poly and 4-metal process. Findings – The post-layout simulation shows that the proposed column driver circuit for LCD driver IC significantly reduces the peak switching current, and it results in the reduction of EMI noise level by more than 15 dB. It is obtained with 20 segmented operations in data latch at 40 MHz frequency. Originality/value – The advantage of the cascode current source is that it can provide a well-controlled bias current with an accurate current transfer ratio. To reduce the EMI noise in LCD driver circuit, the cascode current source is properly located for the DC bias block in the level shifter. The application is rarely done by others, and a significant EMI noise reduction is found. The well-controlled current source provides a high performance switching in the level shifter.

A 1 V CMOS programmable accurate charge pump with wide output voltage range

A 1V, programmable, accurate, high speed, single-ended charge pump is proposed, suitable for low voltage PLLs. It is designed in TSMC 90-nm digital CMOS process and it consists of four switches in a current steering configuration, a unity gain rail to rail buffer for the charge sharing effect elimination, one more rail to rail amplifier for minimizing the DC current mismatch, a programmable current bias circuitry and two drivers based on the standard cell XOR gates specific configuration for achieving good synchronization between all charge pump input pulses at the PLL lock state. Replica biasing technique is applied to all charge pump switches. Current glitches and charge mismatch are suppressed by employing a mechanism with additional switches at the output. It exhibits a maximum DC current mismatch of 1% and charge mismatch of 6% over a wide output voltage range of 0.7V for the entire range of output currents. The wide range of the output voltage remains relatively constant and independent of the selected charge pump current amplitude. This is attained by applying appropriate variation of the W/L ratios of the bias cascode current sources via the employment of additional programmable switches such that their saturation voltages remain relatively constant, something which in turn enables the output currents range to be as wide as it is required.

A Design and Fabrication of a 0.18μm CMOS Colpitts Type Voltage Controlled Oscillator with a Cascode Current Source

In this paper a 2.4GHz CMOS colpitts type microwave oscillator was designed and fabricated using H-spice and Cadence Spetre. There are 140MHz difference between the oscillation frequency and the resonance frequency of a tank circuit of the designed oscillator. The difference is seemed to be due to the parasitic component of the transistor. The inductors used in this design are the spiral inductors proposed in other papers. Cascode current source was used as a bias circuit of a oscillator and the output transistor of the current source is used as the oscillation transistor. A common drain buffer amplifier was used at the output of the oscillator. The measured oscillation frequency and output power of the oscillator are 2.173GHz and -5.53dBm.

A 10-bit Current-steering DAC in 0.35-μm CMOS Process

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-µm CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz .

Linearity performance comparison of cascode current source and single-device current source IDPs; analyses, simulations and measurements

The input differential pair (IDP) is usually a major source of nonlinear distortion in any op-amp. This is especially true if the input signal has a large common-mode component, as is the case when an op-amp functions as a unity-gain buffer or as part of a single-ended sample-hold (S/H) circuit. In this paper, we analyse the distortion of the commonly used cascode current source IDP structure and explain the sources of its nonlinear behaviour. Next, a special design technique is proposed which enhances the linearity of IDPs. The circuit uses a single device current source that has the same channel length while its width is double those of IDP devices. Theoretical analysis, as well as simulation and experimental results, is given to confirm the improved linearity of a unity gain buffer. Simulations predict improvements up to 20 dB. 15 dB total harmonic distortion (THD) reduction was also achieved for a 15 MHz input signal based on measurement of a test chip. The method is valuable as power supply voltages shrink, and the design offers extra voltage headroom at input.

A 3 V 10 b 100 MS/s digital-to-analog converter for cable modem applications

This paper describes a 10 b 100 MS/s CMOS digital-to-analog converter (DAC) for cable modem applications. Differential switches with the proposed deglitching circuit and the cascode current sources, separated from the unit decoded current cell matrix improve the dynamic performance. The proposed and conventional prototype DACs are fabricated in a 0.35-/spl mu/m CMOS process. The measured differential and integral nonlinearities of the proposed DAC shows /spl plusmn/0.17 LSB and /spl plusmn/0.43 LSB at a 10 b level, respectively. At 100 MS/s, the spurious-free dynamic range is 66 dB for a 100 kHz input signal and 52 dB for a 10 MHz input signal.

3 V 10 b 70 MHz CMOS D/A converter for video applications

This work describes a 10 b 70 MHz CMOS digital-to-analogue converter (DAC) for video applications. The proposed DAC is composed of a unit decoded matrix for 7 MSBs and a binary weighted array for 3 LSBs, considering linearity, power consumption, routing area and glitch energy. A new switching scheme for the unit decoded matrix is developed to further improve the linearity. Cascode current sources and differential switches with a new deglitching circuit improve the dynamic performance.