Design of 8-Bit Hybrid Current Steering Digital to Analog Converter in a Standard 65nm CMOS Technology

Abstract

A digital-to-analog converter (DAC) in electronics is a device that transforms digital signals into analog signals. There are various DAC architectures, and DAC's usefulness for a given application is determined by factors like resolution, INL, DNL, power consumption, maximum sampling frequency, and others. Because digital-to-analog conversion may damage a signal, a DAC with negligible faults for the application should be used. The current-steered digital-to-analog converter is well suited for high-speed applications because no buffers are needed for current steering architectures and the output is the total current drawn from the supply. In this paper, an 8-bit hybrid current steering digital-to-analog converter is proposed. Four cascode current sources with different weights are used in this architecture. The UMC 65nm CMOS technology was used to design the digital-to-analog converter. The INL and DNL were +0.19/-0.15 LSB and +0.28/-0.11 LSB respectively. The DAC uses roughly 3.25 mW at a supply voltage of 1.2V and a sample rate of 100 MHz. 12.751 mV was the output voltage at full scale. In comparison to earlier reports, the power, INL, DNL, and chip area used by the digital-to-analog converter in this architecture were significantly lower. It is appropriate for use in portable devices.