Cascaded Gain Stages Research Articles

Generalized Relationship Between Frequency Response and Settling Time of CMOS OTAs: Toward Many-Stage Design

The presence of Pole-Zero (P-Z) pairs in the open-loop frequency response of CMOS OTAs has always been considered detrimental to the closed-loop operation of OTAs. In this work, a new proposed theory is presented showing how to reduce the impact of such P-Z pairs on the settling time of CMOS OTAs - using low-frequency zeros and cascaded-gain stages - consequently revealing un-tapped opportunities for many-stage CMOS OTA design. The proposed theory will be validated and verified through a design example that also demonstrates how the generalized theory unveils opportunities for many-stage OTA design. The presented example is a 2- to 8-stage CMOS OTA based on the TSMC 65 nm CMOS process, verified through simulations (schematic and post-layout) as well as some measurement results.

A high-performance CMOS FDMA for pulsed TOF imaging LADAR system

This paper presents a high bandwidth and low noise fully differential main amplifier (FDMA) for pulsed time-of-flight (TOF) imaging laser detection and ranging application (LADAR), which serves to amplify the small pulse echo signal. The cascaded architecture and active inductor technology are used to enlarge the bandwidth of the circuit and reduce the chip area. The cascaded gain stages, which adopted DC offset isolation circuit, are more robust to the alteration of process. A large bandwidth amplifier (LBA) and an output buffer (OB) structure have been designed to enhance the drive capabilities. Besides, in order to adapt the demand of the LADAR system, the amplifier receiver's bandwidth has been limited by using an inter-stage bandpass filter. Implemented in CSMC CMOS technology, the FDMA chip realizes the -3 dB bandwidth of 730.6 MHz, and an open loop gain of 23.5 dB with the bandpass filter worked. The input-referred noise voltage is 2.7 nV/sqrt(Hz), which effectively reduces the system noise. This chip that occupies 0.25 mmc×0.25 mm in area consumes a power dissipation of 102.3 mW from the 3.3 V power supply. As a part of the integrated chip of the laser radar system, it can better meet the requirements of system.

Low‐power low data rate FM‐UWB receiver front end

This study introduces a frequency modulated ultra-wideband (FM-UWB) receiver optimised for low power and fast start-up. The receiver consists of a front end amplifier converting a frequency modulated signal to an amplitude modulated signal which is applied to an envelope detector. The receiver front end is for 500 MHz channels centred at 3450 and 3950 MHz. The amplifier uses passive gain and four cascaded gain stages to achieve high radio-frequency gain without the need for super-regeneration. By simplifying the architecture this way, the front end has a 5 μs wake-up time to enable efficient duty-cycling. The measured front end receives a signal at −68 dBm while consuming 600 μW of power (excluding a test buffer) from a 1 V supply. Fabrication was done using the IBM 130-nm CMOS technology on a 1 mm × 1 mm loose die.

An inductorless CMOS single‐to‐differential transimpedance amplifier with gain‐enhanced topology and postamplifier

ABSTRACTThis article presents an inductorless single‐to‐differential (S2D) transimpedance amplifier (TIA) with gain‐enhanced topology and postamplifier (PA) for the front‐end of an optical communication receiver. Using the regulated cascode topology with S2D converter, the proposed TIA can avoid the use of extra balance–unbalance (balun) converter. In addition, by incorporating dual active feedback in the cascaded gain stages of PA, the bandwidth of the proposed circuit can be effectively extended without using any inductor. Using a standard 90 nm CMOS process, the proposed circuit exhibits a maximum transimpedance gain of 59 dB Ω and the −3 dB bandwidth of 9.6 GHz. Operated at a supply voltage of 1.2 V, the power consumption of the fabricated circuit is only 45 mW, and maximum usable data rate is 12.5‐Gb/s. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2953–2958, 2014

40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-$\mu{\hbox {m}}$ CMOS

A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cas- code stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms of the operating bandwidth and the gain flatness. With the proposed circuit architecture, two amplifiers are implemented in a standard 0.18-mum CMOS technology. The amplifier with a 3 times 3 configuration exhibits a gain of 16.2 dB and a 3-dB bandwidth of 33.4 GHz, while the one in a form of 2 times 4 demonstrates a gain of 20 dB and a bandwidth of 39.4 GHz. Consuming a dc power of 260 mW from a 2.8-V supply voltage, both circuits provide clear eye-opening with a pseudorandom bit sequence (PRBS) at 40 Gb/s.

Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/performance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-mum CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 muVrms and 163 muVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

A Wideband InP DHBT True Logarithmic Amplifier

A wideband logarithmic amplifier is demonstrated in this paper using InP-InGaAs double heterojunction bipolar transistor technology. The amplifier uses cascaded gain stages including the limiting and unity amplifiers to achieve a piecewise approximation to the ideal logarithmic response. The performance of 43-dB dynamic range, 22-GHz bandwidth, and <plusmn2-dB log error is achieved. The integrated circuit consumes 650 mW and has a chip dimension of 1times0.8 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>

Bandwidth enhancement for transimpedance amplifiers

A technique for bandwidth enhancement of a given amplifier is presented. Adding several interstage passive matching networks enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using well-known low-pass filter component values, is introduced. To demonstrate the feasibility of the method, a CMOS transimpedance amplifier (TIA) is implemented in a 0.18-/spl mu/m BiCMOS technology. It achieves 3 dB bandwidth of 9.2 GHz in the presence of a 0.5-pF photodiode capacitance. This corresponds to a bandwidth enhancement ratio of 2.4 over the amplifier without the additional passive networks. The transresistance gain is 54 dB/spl Omega/, while drawing 55 mA from a 2.5-V supply. The input sensitivity of the TIA is -18 dBm for a bit error rate of 10/sup -12/.

Current noise and photon noise in quantum cascade lasers

A comprehensive model for the photon number fluctuations and the current noise in quantum cascade lasers is presented. It is shown that the photon intensity noise in quantum cascade lasers exhibits little amplitude squeezing even when noise in the drive current is suppressed below the shot noise value. This is in contrast to interband semiconductor diode lasers in which the laser intensity noise can be squeezed well below the shot noise limit by high impedance suppression of fluctuations in the drive current. The theoretical model presented in this paper self-consistently accounts for the suppression of current noise in electron transport in multiple quantum well structures due to various electronic correlations. The nature of these electronic correlations is discussed. Mechanisms responsible for the reduced photon number squeezing in intersubband lasers are elucidated. Scaling of the laser intensity noise and the current noise with the number of cascaded gain stages is also described. Direct current modulation response of quantum cascade lasers is also studied, and it is shown that contrary to the predictions in the literature of terahertz modulation bandwidth for these lasers, bandwidth of almost all quantum cascade lasers that have been reported in the literature is limited by the inverse photon lifetime inside the laser cavity to tens of gigahertz.