Abstract
The presence of Pole-Zero (P-Z) pairs in the open-loop frequency response of CMOS OTAs has always been considered detrimental to the closed-loop operation of OTAs. In this work, a new proposed theory is presented showing how to reduce the impact of such P-Z pairs on the settling time of CMOS OTAs - using low-frequency zeros and cascaded-gain stages - consequently revealing un-tapped opportunities for many-stage CMOS OTA design. The proposed theory will be validated and verified through a design example that also demonstrates how the generalized theory unveils opportunities for many-stage OTA design. The presented example is a 2- to 8-stage CMOS OTA based on the TSMC 65 nm CMOS process, verified through simulations (schematic and post-layout) as well as some measurement results.
Highlights
O PERATIONAL Transconductance Amplifiers (OTAs) are at the core of analog and mixed-signal circuits
A closer look at [16]–[19] reveals the following: (1) the analyses of the relationship between frequency response and settling time were restricted to the case of having a single open-loop P-Z pair only, making them most relevant for 2-stage OTAs, (2) the analyses were based on CMOS technologies that range from line widths greater than 1 micron [16] down to only 0.35 μm [19], without considering more advanced nano-meter scale technology nodes, (3) cascading gain-stages was not a design goal in these works, especially that such older technology nodes allowed supply voltages greater than 3 V, relaxing the need for a multi-stage design
Using the above principle of δC L,i suggested by Eqn (30), the unit-step response of the Nth-order closed-loop Transfer Function (TF) can be approximated with the following expression: 1 y (t) ≈ 1− 1+ N−√1 AZ
Summary
O PERATIONAL Transconductance Amplifiers (OTAs) are at the core of analog and mixed-signal circuits. A closer look at [16]–[19] reveals the following: (1) the analyses of the relationship between frequency response and settling time were restricted to the case of having a single open-loop P-Z pair only, making them most relevant for 2-stage OTAs, (2) the analyses were based on CMOS technologies that range from line widths greater than 1 micron [16] down to only 0.35 μm [19], without considering more advanced nano-meter scale technology nodes, (3) cascading gain-stages was not a design goal in these works, especially that such older technology nodes allowed supply voltages greater than 3 V, relaxing the need for a multi-stage design. Having an open-loop Transfer Function (TF), which can represent the use of a cascading scheme to build multi-stage OTAs is the starting point
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