Carbon Nanotube Field-effect Transistors Research Articles

Novel extraction method for contact resistance and effective mobility in carbon nanotube field-effect transistors using S-parameter measurements

In this paper, a novel method is presented for the accurate extraction of key parameters of carbon nanotube field-effect transistors (CNTFETs) using S-parameter measurements. An equivalent circuit model, which utilizes lumped components based on the physical characteristics of the device, is employed to model the AC behavior (S-parameters) of the CNTFETs. The proposed method extracts the bias-dependent contact resistance, channel resistance, and gate-channel capacitance from the model at each gate voltage, thereby facilitating the extraction of the effective mobility of the CNT channel. At the last part of this paper, this method is used to quantitatively investigate the impact of electrostatic doping on CNTFETs. This new methodology offers an effective approach for characterizing CNTFETs, which is an important indicator for device optimization. Additionally, the proposed method can be easily applied to other types of FETs.

Based on the comparisons with various types of transistors to predict the trend of nanotube FETs in the future

With the improvement of new technology in electronic devices and the development of nanomaterials, higher better device performance and more efficient functions of Field-Effect Transistors (FETs) are expected, these require the use of material that has well-performed physical and chemical properties. Carbon nanotubes are a viable alternative, and their popularity is increasing rapidly in recent years. With the decrease in the size of the transistor, the increase in current, and the strength of magnetic and electrical fields, many problems for the creation of destructive and leaky currents occurred. This article mainly aimed to summarize three main FET types and included new carbon nanotube FETs by introducing their basic working mechanism and discussing the difficulties such as the short channel effect, gate-induced drain leakage and contact resistance. It also tries to give a few possible solutions to them which include adding a Lightly Doped Drain or using chemical doping, as well as predict how the potential of FETs in the future at the end.

Design of ternary full-adder and full-subtractor using pseudo NCNTFETs

Now-a-days, the binary logic system has intensified by scaling the field effect transistor (FET). However, due to the effectiveness of scaling the FET, ternary logics became more popular. Out of numerous ternary logic devices, carbon nanotube (CNT) FET (CNTFET) is considered a good candidate over silicon FETs. Hence, in this study, ternary schematics are developed based on Pseudo N-type CNTFETs. The ternary basic designs such as standard ternary inverter (STI), AND and OR gates are presented. Then, using the proposed basic logic gates, the complex designs such as full adder and full subtractor are also proposed. The HSPICE simulator is utilized to design proposed circuits and analyze different performance parameters. The performance such as delay, power and power delay product (PDP) are analyzed for the proposed circuits. Moreover, the proposed schematics performances are also compared to complementary schematics. It investigated that Pseudo N-type CNTFET schematics improved the overall performance on an average up to 65.82% over the complementary ternary circuits.

Biotemplated precise assembly approach toward ultra-scaled high-performance electronics.

Structural DNA nanotechnology can be programmed into complex designer structures with molecular precision for directing a wide range of inorganic and biological materials. However, the use of DNA-templated approaches for the fabrication and performance requirements of ultra-scaled semiconductor electronics is limited by its assembly disorder and destructive interface composition. In this protocol, using carbon nanotubes (CNTs) as model semiconductors, we provide a stepwise process to build ultra-scaled, high-performance field-effect transistors (FETs) from micron-scale three-dimensional DNA templates. We apply the approach to assemble CNT arrays with uniform pitches scaled between 24.1 and 10.4 nm with yields of more than 95%, which exceeds the resolution limits of conventional lithography. To achieve highly clean CNT interfaces, we detail a rinsing-after-fixing step to remove residual DNA template and salt contaminations present around the contact and the channel regions, without modifying the alignment of the CNT arrays. The DNA-templated CNT FETs display both high on-state current (4-15 μA per CNT) and small subthreshold swing (60-100 mV per decade), which are superior to previous examples of biotemplated electronics and match the performance metrics of high-performance, silicon-based electronics. The scalable assembly of defect-free three-dimensional DNA templates requires 1 week and the CNT arrays can be synthesized within half a day. The interface engineering requires 1-2 d, while the fabrication of high-performance FET and logic gate circuits requires 2-4 d. The structural and performance characterizations of molecular-precise DNA self-assembly and high-performance electronics requires 1-2 d. The protocol is suited for users with expertise in DNA nanotechnology and semiconductor electronics.

Physics-Integrated Machine Learning for Efficient Design and Optimization of a Nanoscale Carbon Nanotube Field-Effect Transistor

We propose an efficient framework for optimizing the design of Carbon Nanotube Field-Effect Transistor (CNTFET) through the integration of device physics, machine learning (ML), and multi-objective optimization (MOO). Firstly, we leverage the calibrated TCAD model based on experimental data to dissect the physical mechanisms of CNTFET, gaining insights into its operational principles and unique physical properties. This model also serves as a foundation, enabling multi-scale performance evaluations essential for dataset construction. In the ML phase, a chain structure of Support Vector Regression (SVR Chain) guided by a comprehensive statistical analysis of the design metrics is utilized to predict the design metrics. The surrogate model based on the SVR Chain achieves an average mean absolute percentage error (MAPE) of 1.59% across all design metrics without overfitting, even with limited data. The established ML model exhibits its competence in rapidly producing a global response surface for multi-scale CNTFET. Remarkably, an anomalous equivalent oxide thickness (EOT) and ON-state current (I on ) relationship is observed in CNTFET behavior due to extreme gate length scaling in long channel devices. This intriguing observation is further elucidated through a physics-based explanation. We further compare shallow and deep learning-based TCAD digital twins for model selection guidance. Using the Non-Dominated Sorted Genetic Algorithm-II (NSGA-II) in MOO, we harmonize metrics at both device and circuit levels, significantly reducing the design space. The closed-loop framework expedites the early-stage development of advanced transistors, overcoming the challenges posed by limited data.

Highly Stable, Flexible ISFET pH Sensor Using Sorted Semiconducting SWNTs in Aqueous Solution

Flexible sensors enable the gathering of information from nonplanar surfaces, which facilitates huge data collection tasks. Monitoring of pH levels in industrial wastewater is one example. For this purpose, stable, reliable flexible pH sensors are required to monitor pH in pipes or containers. Carbon nanotube field‐effect transistors (CNT‐FETs) are attractive transducers for flexible sensors because of their multiple functionalities, such as good electrical properties and mechanical flexibility. However, semiconducting single‐walled carbon nanotubes (s‐SWNTs) must be separated from metallic SWNTs of high purity for channel materials to be used in CNT‐FETs. Herein, a simple method to sort s‐SWNTs in an aqueous system using only dispersion and centrifugation is developed. This sorting method is much less expensive than other techniques, such as density gradient ultracentrifugation, agarose‐gel chromatography, or selective sorting by conjugated polymers. These sorted s‐SWNTs result in high‐performance CNT‐FETs with electrical hysteresis reduced to almost zero and improved bias stability. This method demonstrates the importance of the solubility parameter between polymers and water for CNT‐FET hysteresis. The resulting carbon nanotubes also have high uniformity of characteristics, making them valuable as transducers for flexible sensors. Furthermore, real‐time pH monitoring using ion‐sensitive, field‐effect transistors (ISFETs) based on CNT‐FET is demonstrated.

Scaling carbon nanotube field effect transistors to 30 nm channel length on pretreated PET

With the extensive application of flexible circuits to artificial intelligence (AI) and the internet of things (IoT), high requirements have been promoted for the integration and miniaturization of flexible circuits. However, the vast majority of transistors on flexible substrates reported so far have micrometer-level channel length (Lch), seriously affecting the integration abilities of flexible circuits. In this work, we explore the scaling behaviors of flexible carbon nanotube field effect transistors (CNT FETs) by fabricating p-type flexible CNT FETs with Lch varying from 2 μm to 70 nm on polyethylene terephthalate (PET) substrates. The improved width-normalized on-state current (Ion/Wch), transconductance (gm) and near-constant gate efficiency indicate that CNTs have great potential in constructing ultra-small flexible FETs. Additionally, we fabricate a CNT FET with a 30-nm channel length on a cleaned PET substrate using a self-aligned top-gate structure; this CNT FET can achieve a high on-state performance of 103 μA/μm when Vds = −0.8 V. The pitch size of the device is 230 nm, which is the smallest size of flexible transistors so far. Even with deep submicron and nanometer channel lengths, the yields of flexible CNT FETs can reach 60% (33/56); which is benefiting from the pretreated substrate, demonstrating the potential for large-scale production.

Sensitive and rapid detection of bacterial endotoxin with a functional carbon nanotube field-effect transistor biosensor

Endotoxin in the blood can cause unexplained fever, and even death due to endotoxemia and bacteremia. Rapid and sensitive detection of endotoxin has become a priority event to intervene in the occurrence of dangerous diseases in time. In this context, a carbon nanotubes-based field-effect transistor (CNTs FET) nanosensor is developed to realize the rapid, label-free and sensitive detection of endotoxin. The CNTs FET was fabricated by assembling the polymer-sorted high-purity semiconductor CNT films onto the sensing channel. In order to improve the detection sensitivity, carboxylated graphene quantum dots (cGQDs) were coupled to the CNT surface via the poly-l-lysine (PLL). After that, polymyxin B (PMB), which is highly specific for endotoxin, was covalently combined with cGQDs, thus enabling the capture and detection of endotoxin. The method not only displayed an extremely low level of limitation of detection in PBS (4.6 fg/mL) and serum (30.3 fg/mL), respectively, with superior resistance to interference, but also enabled the analysis of Gram-negative bacterial infections in blood samples in a short duration of time. Meanwhile, the receiver operating characteristic curve (ROC) proved the superior diagnostic accuracy of this method (AUC = 0.990). Considering its excellent performance, the constructed CNTs FET biosensor is a promising tool to provide early warning of disease for clinical Gram-negative bacteremia and endotoxemia.

A unique universal block in QCA technology

The limitations of Complementary Metal Oxide Semiconductor (CMOS) such as high-power dissipation, short channel effects, and high lithography has prompted scientists to look forward to alternatives. Many nanotechnologies were emerged and still in the competition such as Fin Field-Effect Transistor (FinFET), Carbon Nanotube Field-Effect Transistor (CNFET), Quantum-dot Cellular Automata (QCA). QCA is a new nanoelectronics technology used a new method for calculations and it is a promising technology in terms of power dissipation. In QCA, circuit complexity is depending on cell count, area and latency. For commercial purposes a universal gate is necessary, this gate can be used alone to design any Boolean function, where in CMOS technology, the NAND or NOT gates have the ability to be a universal gate. The dominant gates in QCA are the majority gate with inverter where QCA circuits cannot be designed using only a universal gate. Because the structure of the gate is important in QCA, this paper introduces a new low complexity singular block that can be used as a universal block. The proposed block can be used to form AND, OR, NOT, Exclusive-OR (XOR) and Multiplexer (MUX). So, this block not just used to design any circuit but also it can be used to form other important functions XOR and MUX to build large circuits in an optimum form.

Additive Influence of Top Metal Contact and Alumina Deposition on the Threshold Voltage of Suspended Carbon Nanotube Field-Effect Transistors.

One-dimensional nanostructures such as carbon nanotubes offer excellent properties useful for applications in gas sensors, piezoresistive devices, and radio frequency resonators. Considering their nanoscale form factor, carbon nanotubes (CNTs) are highly sensitive to surface adsorbents. This study presents the fabrication flow of CNT devices with extended passivated areas around electrical contacts between the CNT and source and drain electrodes. These types of structures could help in understanding the intrinsic CNT response by eliminating the analyte impact on the Schottky barrier regions of the CNT field-effect transistors (CNTFETs). The influence of multiple processing conditions on the electronic properties of CNTFETs with a suspended individual CNT used as the CNTFET channel is presented. Our findings show a threshold voltage shift in CNT ISD-Vg characteristics following the metal deposition and alumina atomic layer deposition.

Power efficient designs of CNTFET-based ternary SRAM

This paper presents three new power-efficient designs of ternary SRAM using carbon-nanotube-field-effect-transistors (CNTFETs). Two of the proposed ternary SRAM designs are cycle-operator based and the third design is buffer-based. The cycle operators and buffer used in the design of the proposed ternary SRAM consume low power as they use two power supplies for operation. Ternary logic implementation using CNTFETs is largely being used lately due to the advantages it provides in terms of reduced interconnect complexity and chip area. The proposed ternary SRAM designs are compared with the existing designs using HSPICE simulations that use a standard Stanford CNTFET model. All the three proposed designs show considerable improvement in power consumption for read and write operations than their existing counterparts in literature. The read, and write delays and noise margins of the proposed designs are also analysed and are found to be comparable to the existing designs.

A low-power high speed full adder cell using carbon nanotube field effect transistors

The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model is simulated using 32 nm with CNTFET technology, a voltage supply of +0.9V. Performance comparisons between various proposed designs and existing 1-bit full adder design have been made in terms of the delay, power, and power delay product (PDP). The proposed CNFET logic also design for n-bit carry look adder (CLA) and compare it to other CLAs to evaluate performance and reliability. The simulation results shows that the proposed adder consume less power than existing adders.

An efficient GNRFET-based circuit design of ternary half-adder

Attaining low energy consumption in digital circuits design is a main task for designers because emerging applications are based on batteries and face limited-energy. Designing digital circuits with application to multiple-valued logic (MVL) and graphene nanoribbon field-effect transistor (GNRFET) provides a huge improvement in energy consumption. In this regard, this paper presents a novel ternary Half-Adder (THA) implemented with metal-oxide semiconductor (MOS)-type GNRFET. In the proposed THA, the Sum circuit is based on a combination of 3:1 ternary multiplexer, unary operators, and two supply voltages (dual-VDD), and the Carry circuit is based on unary operators, pass-transistor logic, and dual-VDD. The proposed THA is simulated using the 32-nm MOS-type GNRFET technology node at 0.9 V supply voltage in the HSPICE simulator. The proposed THA reduces the transistors count by 5.71–26.67% compared to the previously published THA circuits available in the literature, which are similar to the proposed THA from the design approach point of view. It is concluded from the simulation results that the proposed THA improves the power and energy consumptions by 83.33–91.41% and 66.38–82.27%, respectively. Moreover, the proposed THA is also designed and simulated using the Stanford 32-nm carbon nanotube field-effect transistor (CNTFET) technology. The proposed MOS-type GNRFET-based THA reduces the power and energy consumptions by 84.79% and 68.03%, respectively, and increases the delay by 2.12 × compared to its CNTFET-based counterpart. Moreover, the proposed CNTFET-based THA offers the second-lowest delay and power and the third-lowest energy compared to other existing CNTFET-based THA circuits.

Design of Three-valued Logic Based Adder and Multiplier Circuits using Pseudo N-type CNTFETs

This work presents a novel technique to develop the three-valued logic (TVL) circuit schematics for very large-scale integration (VLSI) applications. The TVL is better alternative technology over the two-valued logic because it provides decreased interconnect connections, fast computation speed and decreases the chip complexity. The TVL based complicated designs such as half-adder and multiplier circuits are designed utilizing the Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The proposed TVL half adder multiplier schematics are developed in HSPICE tool. Additionally, the delay and circuit area for the half- adder and multiplier circuits are investigated and compared to the complementary circuits. The memory usage and CPU time for the proposed circuits are also analyzed. It is observed that the proposed circuit designs show the improved performance up to 43.03% on an average over the complementary designs.

Optimization of Double-Gate Carbon Nanotube FET Characteristics for Short Channel Devices.

Transistors are the fundamental electronic component integrated into electronic devices' chips Carbon Nano Tube (CNT) based field. Effect Transistor (FET) is a promising component for next-generation transistor technologies; as it has high carrier mobility, device stability, and mechanical flexibility. Nevertheless, some shortcomings in the CNT FET's design prevent it from providing the best performance while preserving thermal stability. The structure and functionality of transistors with Double-Gate (DG) devices, which use carbon nanotubes as active channel regions, have been examined by the authors of this study. The DG CNT FET has been extensively simulated using an electronic device simulator with various device geometrics, including channel length, oxide thickness for its output, and transfer characteristics. In comparison to reported patents and published works, this demonstrates a significant improvement Conclusion: A new perspective on the DG CNT FET's device performance characteristics is provided by this research work, which can be scaled down to minimum channel length without Short Channel Effects (SCEs).

A high‐capacity and nonvolatile spintronic associative memory hardware accelerator

AbstractSignificant progress has been made in manufacturing emerging technologies in recent years. This progress implemented in‐memory‐computing and neural networks, one of today's hottest research topics. Over time, the need to process complex tasks has increased. This need causes the emergence of intelligent processors. A nonvolatile associative memory based on spintronic synapses utilising magnetic tunnel junction (MTJ) and carbon nanotube field‐effect transistors (CNTFET)‐based neurons is proposed. The proposed design uses the MTJ device because of its fascinating features, such as reliable reconfiguration and nonvolatility. At the same time, CNTFET has overcome conventional complementary metal‐oxide‐semiconductor shortcomings like the short channel effect, drain‐induced barrier lowering, and poor hole mobility. The proposed design is simulated in the presence of process variations. The proposed design aims to increase the number of weights generated in the synapse for higher memory capacity and accuracy. The effect of different tunnel magnetoresistance (TMR) values (100%, 200%, and 300%) on the performance and accuracy of the proposed design has also been investigated. This investigation shows that the proposed design performs well even with a low TMR value, which is very important and remarkable from the fabrication point of view.

Design of CNTFET-based Ternary Ring and Up–Down Counter Cells

In recent times, the multi-valued logic (MVL) design has been widely explored in the designing of digital computing circuits as the goals of enhanced processing capability with reduced interconnect complexity and small chip area are achieved. Hence, this work describes the design methodology of ternary logic-based asynchronous and synchronous up-counter, down-counter, and ring-counter designs using D-flip-flops in carbon nanotube technology. Carbon nanotube-field-effect transistors (CNTFETs)’ unique feature of altering the device threshold voltage by making variations in CNT diameter is exploited for the realization of multiple voltages in ternary logic design. Here the principle of the master-slave scheme is adopted for the designing of Dual shift-single shift and Single shift-dual shift-D-flip-flop circuits using the cyclic property of shifting operators. These flip-flop designs are further extended to construct multiple-digit counter structures which are suitable for realizing the logic functionality of up-counter, down-counter, and ring-counter designs. To exploit ternary logic increased computation capability benefit, a mode control up/down counter circuit is designed in which a single module is generating up and down-counting sequence based on applied mode input. To investigate the performance of the proposed designs, the simulations are performed using the Synopsys HSPICE simulator considering the 32 nm Stanford CNTFET model. According to the simulation results, a maximum energy consumption reduction up to 55% is obtained compared to the counterpart. Hence, the increased computational capability of three-valued logic is exploited in the presented work to achieve energy enhancements in designing ternary sequential circuits.

Serum CRP biomarker detection by using carbon nanotube field-effect transistor (CNT-FET) immunosensor

C-reactive protein (CRP) is produced by the liver in response to systemic inflammation caused by bacterial infection, trauma and internal organ failures. CRP serves as a potential biomarker in the precise diagnosis of cardiovascular risk, type-2 diabetes, metabolic syndrome, hypertension and various types of cancers. The pathogenic conditions indicated above are diagnosed by an elevated CRP level in the serum. In this study, we successfully fabricated a highly sensitive and selective carbon nanotube field-effect transistor (CNT-FET) immunosensor for the detection of CRP. The CNTs were deposited on the Si/SiO2 surface, between source-drain electrodes, afterwards modified with well-known linker PBASE and then anti-CRP was immobilized. This anti-CRP functionalized CNT-FET immunosensor exhibits a wide dynamic detection range (0.01–1000 μg/mL) CRP detection, rapid response time (2–3 min) and low variation (<3 %) which can be delivered as a low-cost and rapid clinical detection technology for the early diagnosis of coronary heart disease (CHD). For the clinical applications, our sensor was tested using CRP fortified serum samples and sensing performance was validated using enzyme-linked immune-sorbent assay (ELISA). This CNT-FET immunosensor will be helpful in taking over the complex laboratory-based expensive traditional CRP diagnostic procedures practiced in the hospitals.

Towards Nonvolatile Spintronic Quaternary Flip-Flop and Register Design

The exciting properties of multi-valued logic (MVL) in overcoming the limitations of binary systems have led to widespread research on this topic. Considering various types of MVL, quaternary logic is more compatible with the existing binary systems. This paper proposes a nonvolatile quaternary flip-flop (NQFF) based on the unique features of the carbon nanotube field-effect transistors (CNTFETs) and magnetic tunnel junctions (MTJs). The proposed NQFF utilizes Spin-Hall effect (SHE)-assisted spin-transfer torque (STT) MTJs to provide nonvolatility with lower write energy, and multi-Vt gate-all-around (GAA) CNTFETs offer higher performance. On the other side, due to the usage of a shadow latch and the design of the proposed circuit, the delay of MTJ switching does not affect the delay of the whole circuit. The simulation results show that the proposed NQFF offers 50% lower PDP when the system is idle for only 25% of its total operational time.

High performance quaternary logic designs using GNFETs

The implementations of quaternary circuit schematics are presented in this paper. The quaternary logic is a better choice over the conventional logics because it offers high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented to design quaternary schematics using graphene nanoribbon field effect transistors (GNFETs). The dimer line of graphene nanoribbon (GN) is used to control the threshold voltage of GNFETs. Four quaternary logic inverter circuits such as standard quaternary inverter (SQI), intermediate quaternary inverter (IQI), positive quaternary inverter (PQI) and negative quaternary inverter (NQI) along with the NAND and NOR circuits are proposed. Furthermore, the quaternary half adder circuit is designed that helps to develop complex designs. The HSPICE simulator is utilized for simulating the proposed designs to obtain the performances such as delay, power and power delay product (PDP). The obtained circuit performances are compared with carbon nanotube FETs (CNFETs) based circuits. The comparison results show that the proposed GNFET circuits achieved 53.51% of overall performance improvement over the CNFET circuits.