ABSTRACT Multilevel Inverters (MLIs) have gained widespread acceptance in high-power conversion due to their distinctive features, including minimised harmonic distortion in the output and reduced voltage stress on power switches. Nevertheless, including numerous DC sources and switches in MLIs increases costs and system complexity. To address this challenge, this paper introduces a hybrid MLI topology featuring a reduced device count suitable for symmetrical and asymmetrical source configurations. The proposed hybrid MLI topology (PHMLIT) can produce a 9-level output voltage with a symmetrical configuration and 7- or 11-levels output voltage with an asymmetrical configuration. Moreover, the cascaded connection of the cells of the PHMLIT generates a broad range of voltage levels across the output. Additionally, a novel switching strategy is devised to minimise the size of the capacitor. The comparative analysis illustrates that the PHMLIT exhibits superior characteristics compared to conventional and recently developed topologies regarding the number of switches, DC sources, diodes, capacitors, and total blocking voltage (TBV). Finally, the feasibility of the PHMLIT is confirmed through various simulation and experimental tests.
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