A new triple voltage gain seven level switched capacitor-based inverter with minimum voltage stress

Abstract

Abstract This paper presents, a new seven level triple voltage gain inverter topology is proposed based on switched capacitor technique. The proposed inverter topology has minimum voltage stresses on the switches and balanced capacitor voltages. This paper briefs the operation of proposed topology, voltage stress analysis, capacitor sizing and generation gate signals for the switches. In addition, proposed topology is modeled in industrial based software PLECS with practical switches to study thermal behavior and efficiency analysis. Further, the proposed inverter topology is compared with competitive topologies in the recent literature. The proposed topology has merits like minimum total standing voltage, switching redundancy and inherent polarity generation. Furthermore, MATLAB based simulations and experimental analysis is done to validate the superior performance the proposed topology. The experimental results for the proposed seven-level inverter are presented and discussed in brief by considering different types of loads, amplitude modulation variations and frequency variations.