Capacitor-less Low-dropout Regulator Research Articles

A 600-mA Multifeedback Loop Capacitorless Low-Dropout Regulator With a –40-dB Power Supply Rejection at 1 MHz With 27.5-μA Quiescent Current Consumption

A 600-mA Multifeedback Loop Capacitorless Low-Dropout Regulator With a –40-dB Power Supply Rejection at 1 MHz With 27.5-μA Quiescent Current Consumption

A 0.91-[formula omitted]A-quiescent-current capacitor-less LDO with sub-threshold transient enhancement and bulk-driven feed-forward supply ripple cancellation

This paper presents a capacitor-less low-dropout (OCL-LDO) regulator that features a low quiescent current for low power applications. To enhance the transient response of proposed OCL-LDO, a sub-threshold transient enhancement circuit including a transient signal input stage, a current subtractor, and a current amplifier is suggested. Meanwhile, a circuit made up of a bulk-driven ripple feed-forward circuit and a ripple introduction circuit is developed in order to improve PSR of the OCL-LDO. The proposed OCL-LDO is fabricated in 0.18 μm standard CMOS process and has an active area of 0.053 mm2. Based on measurement results, the proposed OCL-LDO has a maximum load current of 100 mA at 1.2 V input and 1 V output, and a minimum quiescent current of 0.91 μA. The overshoot voltage and undershoot voltage are 199 mV and 204 mV, respectively. PSR of the OCL-LDO is −71.8 dB at 1 KHz when the load current is 100 mA. Furthermore, the OCL-LDO exhibits a load regulation of 11.1 μV/mA and a line regulation of 1.05 mV/V.

Capacitor-Less Low Dropout Regulator Development Research

Capacitor-Less Low Dropout Regulator Development Research

A Fast Transient Response Capacitor-Less LDO with Transient Enhancement Technology.

This paper proposes a fast transient load response capacitor-less low-dropout regulator (CL-LDO) for digital analog hybrid circuits in the 180 nm process, capable of converting input voltages from 1.2 V to 1.8 V into an output voltage of 1 V. The design incorporates a rail-to-rail input and push-pull output (RIPO) amplifier to enhance the gain while satisfying the requirement for low power consumption. A super source follower buffer (SSFB) with internal stability is introduced to ensure loop stability. The proposed structure ensures the steady-state performance of the LDO without an on-chip capacitor. The auxiliary circuit, or transient enhancement circuit, does not compromise the steady-state stability and effectively enhances the transient performance during sudden load current steps. The proposed LDO consumes a quiescent current of 47 µA and achieves 25 µV/mA load regulation with a load current ranging from 0 to 20 mA. The simulation results demonstrate that a settling time of 0.2 µs is achieved for load steps ranging from 0 mA to 20 mA, while a settling time of 0.5 µs is attained for load steps ranging from 20 mA to 0 mA, with an edge time of 0.1 µs.

High PSR external capacitor‐less LDO with adaptive supply‐ripple cancellation technique

AbstractThis work presents an external capacitor‐less low‐dropout regulator (CL‐LDO) with high power supply rejection (PSR) over a wide frequency and load current ( ) range. The high PSR is implemented with an adaptive supply‐ripple cancellation (ASRC) technique. The proposed ASRC circuit consists of a buffer with diode‐connected structure and an adjusting unit. The novel buffer introduces the supply ripple through the diode‐connected transistor to the gate of the pass transistor, enhancing the PSR in the range of 1 MHz. Additionally, the adjusting unit trims the current of the buffer continuously according to the magnitude of to optimize the PSR adaptively. Designed in a 55 nm CMOS process with an input voltage of 1.4 V, the proposed LDO achieves −69 dB and −55 dB PSR at 100 KHz and 1 MHz for 50 mA of , respectively. Moreover, the maximum current efficiency of the LDO is 99.8% at a full of 50 mA.

A 4.65 [formula omitted]V/V line regulation, transient enhanced, capacitor-less LDO with ultra-low load current dependence

A capacitor-less low-dropout regulator (CL-LDO) based on an improved flipped voltage follower (FVF) cell with robust regulation capability and high transient response is presented. The line regulation (LNR) and load regulation (LAR) are enhanced by a stable DC operating point design and multiple feedback loops. A nested feed-forward gm-stage and a nulling resistor in the nested Miller compensation (NGRNMC) topology ensures stability in various challenging conditions. The proposed CL-LDO was designed in 0.18μm BiCMOS technology and occupied an area of 0.0582 mm2, with a typical input voltage range of 3.0 V–3.6 V and a load range of 0–100 mA. Post-simulation verification under various process, voltage, and temperature (PVT) conditions confirms the design’s robustness and reliability. The proposed design achieves the best figure of merit (FoM) of 1.69 mV among state-of-the-art designs, accompanied by a LNR of 4.65 μV/V and a LAR of 27.881 nV/mA.

A 65-nm CMOS Self-Supplied Power Management System for Near-Field Wirelessly Powered Biomedical Devices

This paper proposes a self-supplied power management system to efficiently rectify and regulate the AC voltage received from wireless power transmission techniques to power or recharge biomedical devices. The proposed power management system comprises three integrated functional units, namely, a fully cross-coupled rectifier, a self-biased reference voltage, and a capacitor-less low-dropout regulator (LDO). To reduce the current complexity of designing capacitor-less LDOs, a new architecture based on a pair of diode-connected transistors at the load of the LDO is devised which alleviates the need for a large load capacitor. The proposed power management system is implemented in a 65-nm CMOS process with an active chip area of 0.0810 mm2. Experimental results indicate that this system is capable of rectifying an AC signal up to 5 V at a frequency of 6.78 MHz. This rectified signal is then regulated to a fixed DC voltage of 1.75 V, while the load current can vary between 0 and 75 mA, with a maximum voltage dropout of 170 mV. Advantageously, the proposed power management system is significantly robust to temperature, as a 55 °C change in ambient temperature leads to only a 9% degradation in its overall performance. Furthermore, the ability of the power management system to drive low-power consumer electronics is demonstrated, and its superiority is evidenced by a performance comparison with the latest integrated power management systems presented in the literature.

A Capacitorless LDO Regulator with Fast Feedback Loop and Damping-Factor-Control Frequency Compensation

A fast feedback loop (FFL) based on comparators is proposed in this paper. The FFL improves the transient response characteristics of the output-capacitorless low-dropout (OCL-LDO) regulator. When the load current switches between 1 mA and 100 mA with 1 μs edge time, the overshoot and undershoot are 33 mV and 37 mV, respectively, and recovery time is 1.2 μs and 1.6 μs, respectively. A damping-factor-control (DFC) frequency compensation circuit is used to ensure the stability of the OCL-LDO, and the simulation results show that the phase margin exceeds 50 degree in the entire load variation range. This design is based on 180 nm process, and the area of the chip is 0.068 mm2 (without pads). A band-gap reference circuit is also designed in this work; its output voltage is 1.2 V and its temperature coefficient is 7.96 ppm/∘C. The input voltage range of the proposed OCL-LDO is 2.5 V to 5 V with a linear regulation rate of 0.128 mV/V and a load regulation rate of 0.0017 mV/mA. In addition, the load range of the proposed OCL-LDO is 0 mA to 100 mA, and the minimum required external capacitance is 0 F. The power supply rejection ratio (PSRR) is −46 dB @ 1 kHz.

A 0.6 VIN 100 mV Dropout Capacitor-Less LDO with 220 nA IQ for Energy Harvesting System.

A fully integrated and high-efficiency low-dropout regulator (LDO) with 100 mV dropout voltage and nA-level quiescent current for energy harvesting has been proposed and simulated in the 180 nm CMOS process in this paper. A bulk modulation without an extra amplifier is proposed, which decreases the threshold voltage, lowering the dropout voltage and supply voltage to 100 mV and 0.6 V, respectively. To ensure stability and realize low current consumption, adaptive power transistors are proposed to enable system tropology to alter between 2-stage and 3-stage. In addition, an adaptive bias with bounds is utilized in an attempt to improve the transient response. Simulation results demonstrate that the quiescent current is as low as 220 nA and the current efficiency reaches 99.958% in the full load condition, load regulation is 0.0059 mV/mA, line regulation is 0.4879 mV/V, and the optimal PSR is -51 dB.

A wide input range, external capacitor-less LDO with fast transient response

A high voltage, external capacitor-less low-dropout regulator (HVLDO) with transient enhancement loop is presented in this work. The proposed HVLDO is designed with high withstand voltage laterally-diffused MOS (LDMOS) transistors and a transient enhancement loop is proposed to properly inject/sink current to/from the gate and output nodes of the power transistors to achieve fast transient response and high stability. Fabricated in 0.5µm SOI BCD process, the HVLDO occupies an active area of 0.29mm2. Operating with an input voltage ranging from 5.2 to 20V, it supplies an output voltage of 5V and a maximum load of 100mA. For all load conditions, this design has the power supply rejection of -49dB@100kHz, the phase margin over 68.4deg and achieves a temperature coefficient of 13.15ppm/°C. Measurement results show that this design has a line regulation of 0.88mV/V and a load regulation of 0.22mV/mA. The proposed HVLDO features fast line transient response of 60/20mV@9.8V/µs, fast load transient response of 30/70mV@100mA/µs, and recovery time of 2µs without external capacitors. Compared with the prior art, this work achieves the best transient FOM of 12.19fs.

A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively.

Design of capacitor-less LDO regulator with SCR-based ESD protection using dual push-pull stage

ABSTRACT The external capacitors of conventional LDO (Low Drop Out) regulator have a function to improve the transient response characteristics affected by the overshoot and undershoot. However, the LDO regulator proposed in this study is replaced the function of the external output capacitor with a dual push-pull stage and is achieved a fast transient response by a newly added control path to replace the function of the capacitor removed along with the existing feedback path. The proposed LDO regulator can also be provided the improved ESD (Electro Static Discharge) robustness characteristics by applying the SCR (Silicon Control Rectifier)-based ESD (Electro Static Discharge) protection device embedded into the output node and power line. The LDO regulator with dual push-pull circuit proposed in this study was operated at a maximum load current of 100 mA, an output voltage of 3 V, and an input voltage range of 3.3 ~ 4.5 V. As a result of the measurement, an undershoot voltage of 110 mV and an overshoot voltage of 123 mV were maintained when a load current of 100 mA was applied. Further, the ESD robustness characteristic of HBM is guaranteed at 8kV or higher.

Design of high-reliability LDO regulator with SCR based ESD protection circuit using body technique and load transient detection

External capacitors in conventional LDO regulators can reduce transient response characteristics such as overshoot and undershoot. However, the capacitor-less LDO regulator proposed in this study achieves the transient response improved by applying body technique to the pass transistor, thereby provides the high areal efficiency and excellent current driving capability, and shows the improved ESD robustness characteristics. Also, the proposed ESD protection device based on due to the SCR (Silicon Control Rectifier) built into the output node and the power line. As a result, it was confirmed that the transient response characteristics of the proposed LDO regulator were improved and free space could be secured by applying the body technique of the pass transistor. The operating conditions of the proposed LDO regulator were set as an input voltage varying from 3.3V to 4.5V, a maximum load current of 200mA, and the output voltage of 3V. As a result of the measurement, when the load current was 200mA, the voltage was found to be 23mV in the undershoot state and 29mV in the overshoot state. In addition, the ESD robustness characteristic of HBM is secured at 8kV or higher.

Design of Capacitor-Less High Reliability LDO Regulator with LVTSCR Based ESD Protection Circuit Using Current Driving Buffer Structure

The peak voltage depending on the load current can be affected by the external capacitors installed in the output stage of the LDO regulator. However, the capacitor-less LDO regulator proposed in this study was applied a current driving buffer structure between the output stage of the error amplifier and the path transistor. Therefore, the proposed LDO regulator maintained a stable output voltage regardless of the load current by controlling an effective overshoot/undershoot voltage. In addition, the proposed LDO regulator has a built-in LVTSCR based on the ESD protection circuit. As most IC circuits are malfunctioned and destroyed by the ESD phenomenon, the reliability was verified through the built-in ESD protection circuit of the proposed LDO regulator. The proposed LDO regulator with the current driving buffer structure can effectively control the peak voltage. As a result of the measurement, the undershoot voltage of 22 mV and the overshoot voltage of 19 mV were maintained when the load current of 250 mA was provided under the conditions of 3.3 V to 4.5 V and the output power voltage of 3 V. The proposed ESD protection circuit is also guaranteed to function at temperatures as high as 500 K.

A three‐stage capacitor‐less low noise LDO regulator for DCO phase noise reduction

A phase noise reduction technique is presented in a three-stage capacitor-less (CL) low dropout (LDO) regulator. This paper proposes a simple RC network that reduces the noise from both bias generation and inside the LDO. This LDO is applied to a conventional CMOS LC oscillator and achieved 3 dB reduction of phase noise at 1 MHz offset from 20 GHz output. The line and load regulations are, 90 μV/V and 0.013 μV/mA, and the output noise at 1 MHz is 6.6 nV / Hz ${\rm{nV}}/\sqrt {{\rm{Hz}}} $ .

0.6-V-V IN 7.0-nA-I Q 0.75-mA-I L CMOS Capacitor-Less LDO for Low-Voltage Micro-Energy-Harvested Supplies

A capacitor-less (CL) low-dropout (LDO) regulator suitable to be incorporated in an on-chip system with low-voltage micro-energy-harvested supply, is proposed in this contribution. The differential input stage of the error amplifier includes bulk-driven MOS transistors, thus providing the LDO with an output voltage range that extends from the negative rail up to a level very close to the input voltage without the need of using a resistive feedback network. The circuit parameters relying on the feedback factor, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> , are maximized thanks to the use of a unitary value for this parameter. The CL-LDO has been designed and fabricated in standard 180-nm CMOS technology and optimized to operate with an input voltage equal to 0.6 V and a reference level of 0.5 V. The experimental characterization of the fabricated prototypes shows that, under these operating conditions, the LDO is able to deliver a load current above 0.75 mA with a total quiescent current of only 7.0 nA. Furthermore, the proposed voltage regulator is able to operate from input voltages as low as 0.4 V, delivering in this case a maximum load current of 30 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> .

A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a −40 to 120 °C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

A 310-nA Quiescent Current 3-fs-FoM Fully Integrated Capacitorless Time-Domain LDO With Event-Driven Charge Pump and Feedforward Transient Enhancement

In this article, a fully integrated capacitorless low-dropout regulator (LDO) is presented for Internet-of-Things (IoT) edge sensor application. To achieve sub-1-V operation and fast transient response with low quiescent current, the conventional operational transconductance amplifier (OTA)-based error amplifier (EA) is replaced with oscillator-based voltage-to-time converter and time-domain signal processing, including time-domain edge-based frequency comparator (FC) and event-driven voltage mode charge pump (CP). Compared with the conventional phase frequency detector (PFD), the proposed clock-edge-based FC achieved more than six times power reduction. Event-driven CP is adopted to drive analog power transistor and the transient response is enhanced by feedforward capacitor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {FD}}$ </tex-math></inline-formula> and coarse–fine CP control. To further reduce the power consumption, multi-voltage domain and clock frequency optimization are implemented. A prototype chip is fabricated in a standard 65-nm CMOS process. The design only consumes 310-nA quiescent current while achieving 0.5–1.2-V input range, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.0\times 10^{6}$ </tex-math></inline-formula> load dynamic range, and 3-fs figure of merit (FoM).

Design of Capacitor-less LDO applied to Low Power Supply with High-precision Bandgap

This paper proposes a capacitor-less low dropout regulator (LDO) applied to low power supply to meet the needs of low power consumption and highly integration. In order to improve the transient response of the system, a dynamic bias circuit is designed, which can automatically track the change of load current. In addition, the temperature coefficient of bandgap reference in conventional LDO is generally 20-100 ppm/°C. The bandgap reference circuit proposed in this paper can achieve 1.73 ppm/°C without trimming, and the accuracy is better than 1% at all process corner. The design and simulation are based on TSMC 0.18 μm CMOS process, the simulation results show that the LDO output voltage is 1 V when input power supply voltage is 1.2 V. The proposed regulator can operate with a minimum dropout voltage of 200 mV when load current is 50 mA. The maximum undershoot and overshoot voltages are 34 mV and 28 mV, respectively, with 1mA-50mA and 50mA-1mA step load current.

Capacitor‐less FVF low drop‐out regulator with active feed‐forward compensation and efficient slew‐rate enhancer circuit

In this study, an improved capacitor-less flipped voltage follower (FVF) low drop-out regulator (LDO) with active feed-forward compensation (AFFC) and an efficient slew-rate enhancer (SRE) circuit is presented. In capacitor-less FVF LDOs, the dominant pole is placed at the gate of the power metal oxide semiconductor field effect transistor (MOSFET) which demands minimum load current for the feedback-loop to be stable. The proposed compensator has miller compensation along with AFFC which helps to eliminate the minimum load demand for the feedback-loop of the LDO to be stable by shifting the right half-plane (RHP) zero of power MOSFET to left half-plane (LHP) zero. This LHP zero proportionally varies with the first non-dominant pole at the output of the LDO as the load current varies from light load to heavy load and extends the unity gain frequency of the proposed LDO. The SRE circuit supports fast load transients with edge time of 50 ns and achieves less voltage spike without consuming any power at steady-state. This LDO is implemented in 0.18 μ m technology with a drop-out voltage of 200 mV and can drive the load current range of 0–50 mA with regulated output voltages from 1.2 to 1.6 V. It settles faster with the settling time of 250 ns and has the quiescent current of 25.8 μ A .