Capacitive Fingerprint Sensor Research Articles

22.3: Multi‐ Fingerprint Capacitive sensor with Transparent, Low‐cost Solution

A capacitive fingerprint sensor based on panel manufacturing is developed. It enables greater identification at a lower cost. The larger area allows for more feature points to be collected, and Multi‐finger identification can also be realized. Since no optical components are required, the capacitive fingerprint sensor is lighter and thinner than the optical fingerprint sensor. Transparency is also one of its strengths.

P‐5: New Capacitive Active‐Pixel Sensor Based on LTPS‐TFT Backplane Technology for Fingerprint Recognition

We report a new type of capacitive active pixel sensor based on LTPS TFT backplane technology. It is a pixel design method for image sensors, which combines amplifiers and capacitors to form a pixel unit. Each pixel contains three transistors. This structure includes a capacitor as a sensing element, a reset transistor RST (T3), a row selector RS (T1), and a signal amplifier SF (T2). The advantage is to amplify the signal before reading, which is effective reduce the influence of noise and interference sources, so as to achieve high image quality. Based on the new capacitive active pixel sensor, a capacitive fingerprint sensor array was realized and the fingerprint image was successfully captured.

42‐3: Late‐News Paper: Full‐Screen Capacitive Fingerprint Sensor and Touch Sensor

We have developed a novel full screen capacitive fingerprint and touch sensor, which can scan and detect a user's fingerprint anywhere on display, using Low Temperature Poly‐silicon (LTPS) technology and Analog Front End Integrated Circuit (AFE IC) technology. This sensor can detect a fingerprint image with good Signal to Noise Ratio (SNR) through a cover glass, and mode transition from touch sensing to fingerprint sensing, with finger position feedback, in less than 10 msec.

A Sensing Mode Reconfigurable Analog Front-End IC for Capacitive Touch and a-IGZO TFT-Based Active-Matrix Capacitive Fingerprint Sensors

In this paper, we propose a sensing mode reconfigurable analog front-end (AFE) IC for a capacitive touch sensor (CTS) and amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT)-based active-matrix capacitive fingerprint sensor (CFS). The CTS consists of the transmit and receive electrodes for enabling the mutual-capacitance (CM) sensing mode, which can detect the multi-touch. The CFS has the array of a-IGZO TFT and a sensing electrode for enabling the self-capacitance (CS) sensing mode to achieve the high sensitivity. In addition, it can reduce the number of sensing lines by adopting the active-matrix type structure to achieve the low-manufacturing cost. To sense the CTS and CFS, the proposed AFE IC is reconfigured to operate the CM and CS sensing modes, respectively. The proposed AFE IC was fabricated using a $0.13~\mu \text{m}$ CMOS process technology with 20 V high-voltage devices, and demonstrated with a $128\times 72\,\,32$ -inch CTS and a $96\times 96\,\,0.27$ -inch CFS, which represents a pixel resolution of 500 pixel-per-inch. The proposed AFE IC achieves the signal-to-noise ratios of 47.8 dB and 25.0 dB for the CTS and CFS, respectively.

RF Sensor-Based Liveness Detection Scheme With Loop Stability Compensation Circuit for a Capacitive Fingerprint System

A capacitive fingerprint system is the most widely used biometric identification method for smartphones. In this paper, we propose a RF sensor-based liveness detection scheme. This method solves the problem of spoofing attacks, which is a primary disadvantage to capacitive fingerprint sensors. The proposed scheme measures the inherent impedance characteristic difference of the target fingerprint caused by the eddy-current effect with an auto-balancing bridge method. The magnetic field is generated by a small form-factor inductor coil of $\phi =1.5$ mm. This detection scheme can be easily integrated with an existing capacitive fingerprint sensor by using the same CMOS process. The measured results demonstrate the liveness detection capability of the Si-graphite (silicone-graphite) and polyvinyl fake fingerprints that cannot be distinguished by conventional capacitive fingerprint sensors.

Organic Substrate Technologies for Fingerprint Sensors

Fingerprint sensor had a long history. With the mobile electronics security application being ushered in several years back, miniature and low-cost capacitive fingerprint sensors enjoyed an explosion growth. One technology to make such a low-cost, highly sensitive, high environment tolerating and reliable technology is to use organic substrate to construct sensing element. In this paper, several technologies are reviewed. They include Si based absolute capacitive sensors, film-based transcapacitive technology, organic substrate-based transcapacitive technology. To make highly sensitive substrate sensor, a newly invented architecture has been achieved with new photosensitive material in combination with traditional substrate manufacturing process, resulting the best performance at very low cost. Detailed manufacturing process and performance evaluation results will be presented.

CMOS Capacitive Fingerprint Sensor Based on Differential Sensing Circuit with Noise Cancellation.

In this paper, we introduce a differential sensing technique for CMOS capacitive fingerprint detection. It employs a new capacitive-sensing cell structure with charge sharing detection and readout circuit. The proposed technique also can eliminate the effect of parasitic capacitances by employing parasitic insensitive switched-capacitor structure and so increases the sensitivity even under severe noisy conditions. It can also overcome the performance degradation caused by various conditions of finger surface by using a differential integrator and adjusting its number of integrations. In addition, the proposed architecture allows parallel detection of all sensing channels. It can, therefore, substantially speed up the detection process compared with conventional architectures. We implemented a prototype fingerprint sensor chip with an array of 20 × 16 sensor cells using a 130 nm CMOS process. Simulation experiments demonstrated that the proposed architecture provided an SNR gain of 54 dB, whereas a conventional single line sensing gives an SNR gain of only 13 dB.

Transparent and flexible fingerprint sensor array with multiplexed detection of tactile pressure and skin temperature

We developed a transparent and flexible, capacitive fingerprint sensor array with multiplexed, simultaneous detection of tactile pressure and finger skin temperature for mobile smart devices. In our approach, networks of hybrid nanostructures using ultra-long metal nanofibers and finer nanowires were formed as transparent, flexible electrodes of a multifunctional sensor array. These sensors exhibited excellent optoelectronic properties and outstanding reliability against mechanical bending. This fingerprint sensor array has a high resolution with good transparency. This sensor offers a capacitance variation ~17 times better than the variation for the same sensor pattern using conventional ITO electrodes. This sensor with the hybrid electrode also operates at high frequencies with negligible degradation in its performance against various noise signals from mobile devices. Furthermore, this fingerprint sensor array can be integrated with all transparent forms of tactile pressure sensors and skin temperature sensors, to enable the detection of a finger pressing on the display.

Implementation of 144 × 64 Pixel Array Bezel-Less Cmos Fingerprint Sensor

Abstract This paper proposes CMOS integrated 144 × 64 pixel array fingerprint sensor without a bezel electrode. In this paper, the architecture of CMOS capacitive fingerprint sensor readout circuit is presented for general type of a switched capacitive integrator scheme. The pipelined scan driver is included in the fingerprint sensor for fast image capture. It is implemented on 0.35 μm standard CMOS process technology. The operation is validated by SPECTRE for one-pixel and RTL simulation including logic synthesis for a full chip design on condition of 0.35 µm typical CMOS process and 3.3 V power. The layout is performed by full custom flow for sensor cell array and auto P&R for a full chip. The area of a full chip is 4943 μm × 3943 μm and the gate count is 542,000. The area of one-pixel is 48 × 48 µm2. The pitch is 50 µm and image resolution is 508 dpi and power consumption is less than 3 mA.

56‐3: A 500‐dpi Transparent On‐Glass Capacitive Fingerprint Sensor

This paper presents a 500‐dpi transparent on‐glass capacitive fingerprint sensor. On‐glass sensor of 200x200 diamond pattern ITO electrodes are fabricated. High resolution readout ICs which are fabricated on 0.18μm CMOS process achieves 23.5dB SNR on finger touch. This is the first case of transparent on‐glass fingerprint sensor.

Design of 128x8 Pixel Array Fingerprint Sensor with a Capacitive-Sensing Circuit Technique for Image Enhancement

This paper proposes 128x8 array swipe type fingerprint sensor with a capacitive-sensing technique for image enhancement. The circuit of one pixel includes a pixel level chargesharing and charge pump to replace an ADC. The circuit also adopts the circuit technique that improves quality of dry finger image captured with capacitive fingerprint sensor LSIs. The proper operation is validated by HSPICE for one-pixel and RTL simulation including logic synthesis for a full chip design on condition of 0.35μm typical CMOS process and 3.3V power. The layout is performed by full custom flow for one-pixel and auto P&R for a full chip. The area of a full chip is 0.161mm 2 (9013μm x 1781μm) and the gate count is 303,329. The area of one-pixel is 58 x 58 μm 2 . Pitch is 60 μm and image resolution is 423dpi.

A high sensitive MEMS capacitive fingerprint sensor using slotted membrane

In this paper a novel single-chip microelectromechanical systems (MEMS) capacitive fingerprint sensor with slotted membrane is developed to improve the sensitivity. The capacitive sensor consists of a thin, flexible membrane and a rigid back plate with air gap. In this study with making slots in upper electrode to decrease the mechanical stiffness of the membrane, using proportional T-shaped protrusion on diaphragm in order to concentrate the force from finger ridges, making holes in lower electrode to reduce the air damping and using low stress material for diaphragm, we have been succeeded to design a novel MEMS fingerprint sensor with high sensitivity compared with the previous works (Sato et al., IEEE Trans Electron Devices 52:1026–1032, 2005; Damghanian and Majlis, 2008 IEEE International Conference on Semiconductor Electronics (ICSE 2008), pp 634–638 2008). The behaviors of the fingerprint sensor with clamped and slotted membranes are analyzed using the finite element method (FEM). The results yield a sensitivity of 1.44 fF/Mpa for the clamped and 3.22 fF/Mpa for the slotted fingerprint sensor with a 50 × 50 μm2 diaphragm. The sensitivity of the slotted structure is increased 2.236 times.

Design of Novel High Sensitive MEMS Capacitive Fingerprint Sensor

In this paper a new design of MEMS capacitive fingerprint sensors is presented. The capacitive sensor is made of two parallel plates with air gap. In these sensors, the capacitance changes is very important factor. It is caused by deformation of the upper electrode of sensor. In this study with making slots in upper electrode, using T-shaped protrusion on diaphragm in order to concentrate the force from finger ridges, making holes in lower electrode to reduce the air damping and using low stress material for diaphragm, we have been succeeded to design a novel MEMS fingerprint sensor with high sensitivity compared with the previous one. In the present research, simulations were carried out using FEA method.

Impedance-Sensing Circuit Techniques for Integration of a Fraud Detection Function Into a Capacitive Fingerprint Sensor

This paper describes techniques for an impedance-sensing circuit integrated into a capacitive fingerprint sensor to prevent spoofing with a fake finger. We have reported a sensor chip with an embedded impedance-sensing function. We proposed an impedance-sensing circuit that features current-to-voltage con- version using a unity gain buffer. Here, the design of the sensing circuit is discussed. The detectable impedance range and the sensitivity are analyzed within the impedance range for various human fingers. A test chip with the proposed circuit was fabricated using 0.5-μm CMOS/sensor processes. The results confirm that the difference in impedance between a real finger and a fake finger is detected without any degradation of the original characteristics of the fingerprint sensor chip.

Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs

This paper describes a new capacitive-sensing circuit technique that improves the quality of images captured with capacitive fingerprint sensor LSIs. The quality of the captured image depends on the surface condition of the finger. When the finger is dry, the electrical resistance of the finger surface is high. The finger surface resistance induces a voltage drop in the electrical potential of the finger surface (which should be grounded), which leads to poor image quality. To capture clear images even when the finger is dry, the circuit technique improves the image quality using the series resistance caused at the finger surface. The potential of the finger surface is controlled by an enhancement plate and a voltage control circuit. A test chip implementing this technique was fabricated on a 0.5 ?m CMOS process and a sensor process. The chip captures a clear fingerprint image of a dry finger, confirming the effectiveness of the circuit technique for capturing clear fingerprint images independent of the finger surface condition with the capacitive fingerprint sensor LSIs.

Low Parasitic Capacitance and Low-Power CMOS Capacitive Fingerprint Sensor *

In this paper, a low parasitic capacitance and low-power CMOS capacitive fingerprint sensor readout circuit is presented. The side effect of parasitic capacitance has been under control with novel layout structure in sensor cell, and minimal size switch is used to reduce non-ideal effects of MOS switch and achieve good linearity. Power dissipation is also reduced with quiescent current control in buffer amplifier of sensor cell. A prototype chip with 32 × 32 array size has been fabricated using TSMC 0.35μm CMOS process. The chip works at 3.3V power supply and operates at 4MHz clock rate. Capacitance value from 0fF to 60fF can be sensed, corresponding analog output voltage is from 3.02V to 1.57V and the digital output is 6 bits. The overall power consumption is less than 5.5mW.

Analysis and design of a wide micro beam as a pressure gauge for high sensitivity MEMS fingerprint sensors

Sensitivity improvement is a challenging issue in miniature pressure sensors. To improve sensitivity and linearity of the device, a wide micro beam structure has been proposed to gauge capacitance changes caused by the applied pressure in a capacitive MEMS fingerprint sensor. Bending behavior of the device and the effect of the protrusion geometry on partial loading of the micro beam has been analytically investigated. Based on the idea of efficient loading of the wide micro beam, an improved design for the capacitive fingerprint sensor is developed to increase sensitivity. It is shown with FEM simulations that the micro wide beam design is superior to the common membrane based MEMS fingerprint sensors in terms of sensitivity and linearity.

Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI

This paper describes logic and analog test schemes that improve the testability of a pixel-parallel fingerprint identification circuit. The pixel contains a processing circuit and a capacitive fingerprint sensor circuit. For the logic test, we propose a test method using a pseudo scan circuit to check the processing circuits of all pixels simultaneously. In the analog test, the sensor circuit employs dummy capacitance to mimic the state of a finger touching the chip. This enables an evaluation of the sensitivity of all sensor circuits on logical LSI tester without touching the chip with a finger. To check the effectiveness of the schemes, we applied them to a pixel array in a fingerprint identification LSI. The pseudo scan circuit achieved a 100% failure-detection rate for the processing circuit. The analog test determines that the sensitivities of the sensor circuit in all pixels are in the proper range. The results of the tests confirmed that the proposed schemes can completely detect defects in the circuits. Thus, the schemes will pave the way to logic and analog tests of chips integrating highly functional devices stacked on a LSI.

Design and implementation of a capacitive fingerprint sensor circuit in CMOS technology

An ASIC implementation of capacitive fingerprint sensor is described for user authentication on small, thin, and portable equipment. New charge sharing sensing circuit minimizes the influence of internal parasitic capacitances and enlarges the voltage difference between a ridge and valley. A voltage comparator can easily discriminate a ridge and valley. Our method results in about 180% improvement in the voltage difference between a ridge and valley. The sensing circuit also includes a pixel-level automatic calibration scheme. The proposed calibration scheme initializes a capacitive fingerprint sensor LSI to eliminate the influence of the surface condition and environment, which is degraded by dirt during long-time use. The test chip is fabricated on a 0.35 μm standard CMOS 1-poly 4-metal process.

A CMOS integrated capacitive fingerprint sensor with 32-bit RISC microcontroller

The SOC implementation of a capacitive fingerprint sensor, which embeds the 32-bit microcontroller for performing an identification algorithm, is described for user authentication on small, thin, and portable equipment. The SOC is composed of a 160/spl times/192 pixel array with a sensor detection circuit and the embedded 32-bit RISC microcontroller. The proposed sensor detection circuit increases the voltage difference between a ridge and valley about 180% more than conventional detection circuit does and minimizes any electrostatic discharge influence by applying an effective isolation structure. The test chip was fabricated on a 0.35-/spl mu/m standard CMOS 1-poly 4-metal process.