Capacitance Compensation Technique Research Articles

Nonlinear Capacitance Compensation Method for Integrating a Metal–Semiconductor–Metal Varactor with a Gallium Nitride High Electron Mobility Transistor Power Amplifier

A nonlinear capacitance compensation technique is presented in this paper to enhance the linearity of a power amplifier (PA) in the GaN process. The method involves placing an MSM varactor device alongside the GaN HEMT device, which works as the amplifying unit such that the overall capacitance observed at the amplifier input is constant, thus improving linearity. This approach is a reliable and straightforward way to improve PA linearity in the GaN process. The proof-of-concept prototype in this study involves the fabrication of a PA device using a standard GaN HEMT process, which successfully integrates the proposed compensation technique and demonstrates excellent compatibility with existing processes. The prototype has a saturation output power of 18 dBm, a peak power-added efficiency of 51.8%, and a small signal gain of 15.5 dB at 1 GHz. The measured AM–PM distortion at the 5 dB compression point is reduced by more than 50% compared to that of an uncompensated device. Furthermore, the results of third-order intermodulation distortion demonstrate the effectiveness of the linearity enhancement concept, with values improved by more than 5 dB in the linear region compared to those of the uncompensated device. All of the results demonstrate the potential utility of this design approach for wireless communication applications.

A DC-87.8-GHz Switched-Type Attenuator With Switched Capacitor Branch in 40-nm CMOS

This paper presents a 5-bit switched-type attenuator (STA) working from DC to 87.8 GHz. In addition to T-type and Π-type attenuation cells with capacitive compensation technique in shunt branch, a new Π-type-based compensation method with switched capacitor branch is proposed, which effectively reduces phase errors at high frequencies without compromising the amplitude errors. The STA in this work is fabricated in 40-nm CMOS technology and the active core area is 0.019 mm, which demonstrates 15.5-dB attenuation range with 0.5-dB tuning step. Across the operational band, the insertion loss of reference state is 1.4-5.3 dB and the return loss is better than 9 dB for all states. From DC to 87.8 GHz, the RMS amplitude and phase errors are below 0.5 dB and 5.4∘ respectively.

Nonlinear Capacitance Compensation Technique in a Linearity-Enhanced and Broadband GaN PA MMIC for Ku-/K-Band Applications

This article reports on exploiting a nonlinear capacitance compensation technique to achieve high linearity for power amplifier (PA) designs in III–V semiconductor technologies. High linearity is achieved by implementing multiple transistors with deliberate sizes and biasing to compensate for each nonlinear input capacitance behavior. Therefore, the composed PA core acts as one large device where each subdevice is biased individually. Moreover, this approach proves to be a reliable and easy way to improve PA linearity in III–V semiconductor technologies. The viability of this compensation is demonstrated by comparing it to other analog linearity improvement techniques such as derivative superposition. As a proof-of-concept prototype, a 17.2–20.2-GHz class-AB PA is designed in a space-evaluated 150-nm gallium nitride (GaN)-on-silicon carbide (SiC) process. Its capabilities are validated for various modulation bandwidths up to 500 MHz at several frequencies while delivering 32 dBm of output power. The measured third-order intermodulation distortion (IMD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_3$</tex-math> </inline-formula> ) and the fifth-order intermodulation distortion (IMD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_5$</tex-math> </inline-formula> ) are improved by 18 and 25 dB, respectively, compared to a class-AB design. The measured amplitude-to-phase (AM–PM) distortion of less than 0.07 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\circ$</tex-math> </inline-formula> is obtained over the entire bandwidth. Finally, noise-to-power ratio (NPR) results prove the linearity enhancement concept with values better than 15 dB up to maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\rm out}$</tex-math> </inline-formula> . All the results were measured without any applied digital predistortion (DPD).

A DC–28-GHz 7-Bit High-Accuracy Digital-Step Attenuator in 55-nm CMOS

This letter presents an ultrawideband 7-bit digital-step attenuator (DSA). Capacitive compensation technique is utilized to improve the amplitude and phase accuracy and enable wideband operation. The attenuator is implemented in a 55-nm CMOS process and occupies 0.044-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. It demonstrates a 15.9-dB attenuation range with a 0.125-dB step size. The measured insertion loss (IL) is 2.7–6.6 dB at dc–28 GHz and the rms amplitude and phase errors of four measured chips are < 0.15 dB and <0.8°, respectively. The return loss is better than 12 dB for all the 128 attenuation states. To the best of our knowledge, this chip demonstrates the highest attenuation accuracy and minimum phase variation among silicon-based DSAs with a similar dynamic range.

A DC–Ka-Band 7-Bit Passive Attenuator With Capacitive-Compensation-Based Bandwidth Extension Technique in 55-nm CMOS

This article presents a 7-bit wideband passive attenuator with low insertion loss (IL) and high attenuation accuracy in 55-nm CMOS technology. The π-type and bridge-T-type attenuation units utilize an effective capacitive compensation technique, whose bandwidth extension mechanism is detailed in a single-unit pole-zero analysis. The matching-induced performance deterioration is investigated to minimize amplitude and phase errors at the chip level. The fabricated attenuator demonstrates a 32.4-dB attenuation range with a 0.255-dB resolution and a 3.5-8.4-dB IL from dc to 32 GHz. The measured root-mean-square (rms) amplitude and phase errors are below 0.32 dB and 5.33°, respectively. The attenuator occupies a 0.054-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area and consumes negligible power.

A DC-50 GHz CMOS Switched-Type Attenuator With Capacitive Compensation Technique

This paper presents an ultra-broadband 5-bit switched-type attenuator (STA). Three attenuation topologies are employed for the design of the attenuation cells, including the T-type, simplified T-type and $\Pi $ -type topologies. For each attenuation topology, the optimal values of the series and shunt resistors are derived to achieve accurate amplitude tuning and ensure good impedance matching. The capacitive compensation technique is adopted by both the T-type and $\Pi $ -type topologies to enhance the high-frequency performance. Based on the proposed optimization techniques, a systematic design methodology is developed for the STA. The 5-bit STA is implemented in 65-nm CMOS technology and occupies a core chip area of only 0.036 mm2. It exhibits ultra-broadband operation with 15.5-dB amplitude tuning range and 0.5-dB tuning step. The insertion loss of the reference state is 1.5 – 5.9 dB from DC to 50 GHz. The return loss is better than 12 dB for all the 32 states. The RMS amplitude error and phase error are less than 0.25 dB and 3.5° over the DC – 50 GHz band.

3.6‐8.1 GHz CMOS balun with 1.8° in‐band phase difference by using capacitive balance compensation technique

AbstractIn this letter, a passive ultra‐wideband balun with high balance performance is proposed. The balun is realized by using a pair of planar spiral coupled transmission lines and a capacitor which is responsible for the capacitive balance compensation. The straight‐forward scattering matrix derivation shows that the proposed structure can achieve full output balances both in amplitude and phase. For demonstration, two baluns with and without the compensating capacitor were designed and fabricated in a 65‐nm complementary metal‐oxide‐semiconductor (CMOS) process. The measured results show that the compensated balun features a measured insertion loss ≤5.2 dB and a return loss ≥10 dB from 3.6 to 8.1 GHz. Within such a wide frequency range, the measured amplitude and phase difference are ≤0.2 dB and 1.8°, respectively, which are much better than its uncompensated counterpart.

A 6-Bit Ku Band Digital Step Attenuator with Low Phase Variation in 0.13-μm SiGe BiCMOS

A 6-bit Ku band digital step attenuator with low phase variation is presented in this paper. The attenuator is designed with 0.13-μm SiGe BiCMOS process technology using triple well isolation N-Metal-Oxide-Semiconductor (TWNMOS) and through-silicon-via (TSV). TWNMOS is mainly used to improve the performance of switches and reduce the insertion loss (IL). TSV is utilized to provide approximately ideal global current ground plane with low impedance for the attenuator. In addition, substrate floating technique and new capacitance compensation technique are adopted in the attenuator to improve the linearity and decrease the phase variation. The measured results show that the attenuator IL is 6.99–9.33 dB; the maximum relative attenuation is 31.87–30.31 dB with 0.5-dB step (64 states), the root mean square (RMS) for the amplitude error is 0.58–0.36 dB and the phase error RMS is 2.06–3.46° in the 12–17 GHz frequency range. The total chip area is 1 × 0.9 mm2.

Personal Inertial Navigation System Assisted by MEMS Ground Reaction Sensor Array and Interface ASIC for GPS-Denied Environment

A personal inertial navigation system (PINS) assisted by a microelectromechanical systems (MEMS)-based 13 × 26 ground reaction sensor array (GRSA) and a low-power interface application-specified integrated circuit (ASIC) has been designed and demonstrated for GPS-denied environment. The GRSA operating in a contact mode achieves a sensitivity of approximately 3.7 fF/kPa at each sensor node. An electronic interface system, consisting of a capacitance-to-voltage (C/V) converter followed by a correlated double sampling stage, is designed to convert the GRSA capacitance change to an analog output voltage. The analog output voltage is then digitized by a 12-bit cyclic analog-to-digital converter (ADC). Switch capacitance compensation technique is employed to ensure the ADC performance. The ASIC is fabricated in 0.35-μm CMOS process and dissipates a power of 3 mW. The prototype system incorporates a GRSA, an ASIC, and a commercial nine degreeof-freedom (DOF) inertial measurement unit (IMU) in the heel region of a boot. The GRSA can determine an accurate foot-onground timing based on the pressure profiles detected during walking, thus enabling an accurate position calculation and a precise zero velocity update. Furthermore, a system calibration procedure measures the IMU inherent directional drift and scaling factor errors, and compensates them for the navigation data to achieve a superior performance. The prototype system demonstrates a position accuracy of approximately 5.5 m over a navigation distance of 3100 m. The prototype system also achieves a consistent performance over different field tests with various distances and random paths. System characterization results further indicate a tradeoff between sensor array size and system resolution for a given navigation performance requirement, thus providing a design guideline for future system optimization.

A Self-Adaptive Capacitive Compensation Technique for Body Channel Communication.

In wireless body area network, capacitive-coupling body channel communication (CC-BCC) has the potential to attain better energy efficiency over conventional wireless communication schemes. The CC-BCC scheme utilizes the human body as the forward signal transmission medium, reducing the path loss in wireless body-centric communications. However, the backward path is formed by the coupling capacitance between the ground electrodes (GEs) of transmitter (Tx) and receiver (Rx), which increases the path loss and results in a body posture dependent backward impedance. Conventional methods use a fixed inductor to resonate with the backward capacitor to compensate the path loss, while it's not effective in compensating the variable backward impedance induced by the body movements. In this paper, we propose a self-adaptive capacitive compensation (SACC) technique to address such a problem. A backward distance detector is introduced to estimate the distance between two GEs of Tx and Rx, and a backward capacitance model is built to calculate the backward capacitance. The calculated backward capacitance at varying body posture is compensated by a digitally controlled tunable inductor (DCTI). The proposed SACC technique is validated by a prototype CC-BCC system, and measurements are taken on human subjects. The measurement results show that 9dB-16dB channel enhancement can be achieved at a backward path distance of 1 cm-10 cm.

Design of low-loss directional couplers with compensated coupled-line sections in suspended microstrip technique

Design of coupled line 3dB directional couplers realized in suspended microstrip technique has been presented. The main goal was to minimize the insertion losses of the coupler, what has been achieved by a proper choice of the realization technique. As the chosen coupled line geometry is asymmetric to achieve good electrical performance of the resulting coupler, capacitive compensation technique has been utilized to equalize capacitive and inductive coupling coefficients. Furthermore, a distributed-element approach has been investigated for realization of compensation capacitances, due to their physical size resulting from the dielectric structure. The proposed coupler has been designed in two versions, having center frequencies equal to 0.89 and 1.1 GHz, manufactured and measured. The measurement results show good agreement with electromagnetic analyses and prove the correctness and usefulness of the presented design method. The manufactured couplers exhibit insertion losses as low as 0.08 dB at the center frequency.

Experimental Validation of Charge-Sensitive Amplifier Configuration that Compensates for Detector Capacitance

This paper presents measurement results of a method by which the shapes of the output signals derived from a front-end readout circuit can be made insensitive to the input detector capacitance, to a degree limited only by the accuracy with which one can make an amplifier with unity gain. A charge sensitive amplifier including the detector capacitance compensation technique was implemented in a standard 180-nm CMOS technology with a 3.3-V supply voltage. The results show that the technique can successfully mitigate the performance degradation that accompanies large detector capacitance derived from either large-area radiation sensors and/or high permittivity materials, such as nanocrystalline assemblies. In order to verify the feasibility of the technique, we measured alpha particle spectra on two different sized silicon detectors that have detector capacitances of 1.26 pF and 21.84 pF, derived from 2-mm- and 10-mm-diameter devices, respectively. A configuration for integrating the fabricated preamplifier with a detector is also described to exploit the technique for any other application or experiment.

An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

This paper presents an 11-bit 22-MS/s 0.6-mW successive approximation register (SAR) analog-to-digital converter (ADC) using SMIC 65-nm low leakage (LL) CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 × 200 μm2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio (SNDR) is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step.

A 0.007-${\rm mm}^{2}$ 108-${\rm ppm}/^{\circ } {\rm C}$ 1-MHz Relaxation Oscillator for High-Temperature Applications up to 180 $^{\circ } {\rm C}$ in 0.13-$\mu {\rm m}$ CMOS

Reliable high-temperature CMOS oscillators are required for clock or time-base generation in several applications including data acquisition for aerospace, automotive control, oil field instrumentation, and pulp and paper digesters. In this paper, we present low-complexity resistive and capacitive temperature-compensation techniques for CMOS relaxation oscillators. In such oscillators, the frequency of oscillation is a function of a resistor-capacitor product. The resistive compensation technique employs a recently proposed monolithic resistor with a given temperature coefficient (TC) that uses contacts to adjust the TC of the resistor. The capacitive compensation technique is based on using a varactor to adjust the value of the timing capacitance over temperature to compensate for the high-temperature junction leakage current and to keep the oscillation frequency relatively constant. A prototype oscillator based on the proposed techniques is implemented in a standard 0.13-μm CMOS process and reliably operates over 25 to 180 °C. Measured results show that over the temperature range of interest the compensated oscillator achieves a temperature coefficient of 108 ppm/°C. The oscillator along with its output drivers occupies 7200 μm2 (2.3 × to 114 × smaller than state-of-the-art designs) and consumes 428 μW from a 2.5 V supply. For supply variations between 2 and 3 V, the frequency variation is ±1.09%/V.

Development of Ultrabroadband (DC–50 GHz) Wafer-Scale Packaging Method for Low-Profile Bump Flip-Chip Technology

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A <emphasis emphasistype="boldital">locally matched flip-chip</emphasis> (LMFC) interconnect that uses a capacitive compensation technique to minimize impedance mismatch in coplanar waveguide lines is described. With an optimum percentage change in capacitance of 55<formula formulatype="inline"><tex Notation="TeX">$\, \pm \,$</tex></formula>5%, we observe return loss below 25 dB over 90% of a 50 GHz bandwidth. When compared to a conventional flip-chip method, the minimum performance improvement in return loss is 10 dB and the insertion loss is smooth up to 30 GHz. The LMFC interconnect consists of two micromachined features: 1) an air cavity underneath the chip and 2) local trenches in the transition region of the flip-chip interconnect interface. A comparison of different LMFC interconnect designs to the conventional flip-chip approach is made, and design rules to obtain local trench dimensions are discussed. </para>

Improved electronic interfaces for AT-cut quartz crystal microbalance sensors under variable damping and parallel capacitance conditions

A new configuration of automatic capacitance compensation (ACC) technique based on an oscillatorlike working interface, which permits the tracking of the series resonant frequency and the monitoring of the motional resistance and the parallel capacitance of a thickness-shear mode quartz crystal microbalance sensor, is introduced. The new configuration permits an easier calibration of the system which, in principle, improves the accuracy. Experimental results are reported with 9 and 10 MHz crystals in liquids with different parallel capacitances which demonstrate the effectiveness of the capacitance compensation. Some frequency deviations from the exact series resonant frequency, measured by an impedance analyzer, are explained by the specific nonideal behavior of the circuit components. A tentative approach is proposed to solve this problem that is also common to previous ACC systems.

Linearization of CMOS Broadband Power Amplifiers Through Combined Multigated Transistors and Capacitance Compensation

We present the development of a device-level linearization technique and its applications in broadband power amplifiers (PAs). The proposed topology firstly combines derivative transconductance superposition method and gate capacitance compensation technique, and creates a "sweet region" for suppressing third-order intermodulation (IM3) without the penalty of large power consumption. The effectiveness of the proposed technique has been demonstrated through a fully integrated distributed amplifier. The experimental results in 0.18-mum RF CMOS technology show that IM3 is improved by 11 dB. The achievable power-added efficiency is up to 25%, which is the highest among the broadband CMOS PAs reported thus far. The amplifier achieves a measured 3-dB bandwidth of 3.7-8.8 GHz, and a gain of 8.24 dB. The amplifier only consumes 154-mW dc power, and the measured saturation power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) is 19 dBm.

Electrical testing of insulated aerial lifts for contamination using capacitive current compensation technique

The authors introduce a novel method for the measurement of contamination in the insulating arms of aerial lift devices used for live line maintenance work on power lines. Test results from field measurements involving over 120 aerial lifts show that the method gives a direct measure of the contamination level. Comparisons are made as to how the total, capacitive, and resistive currents are affected by the magnitude of contamination as well as the arm orientation and length of the insulating section. The authors also introduce guidelines or criteria for the arm maintenance based on its contamination current level.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A low-power wide-band amplifier using a new parasitic capacitance compensation technique

A 3-mW 800-MHz amplifier with a voltage gain of 10 dB is discussed. The parasitic junction capacitance of a transistor is the major factor limiting the bandwidth particularly for low-power amplifiers. In addition to the pole at the input node, the pole at the output node may become dominant in low-power amplifiers, which use high-speed bipolar transistors. A parasitic capacitance compensation technique to expand the bandwidth in this type of amplifier is discussed. This technique compensates for both capacitances at the input and output nodes and enhances the bandwidth and the gain-bandwidth product. The measured data demonstrate that this technique expands the bandwidth to about twice that of a conventional differential amplifier. In addition, circuit simulation predicts that this technique expands the bandwidth by about 40% over a conventional peaking technique. A stable frequency response without any overpeaking or oscillation problem has been achieved by utilizing the parasitic junction capacitances of dummy transistors as the compensation capacitance. >

Integrated MOS analog delay line

A 16-stage, fixed or variable analog delay line that makes use of integrated p-channel MOS field-effect transistors is described. The delay line relies on `sample' and `hold' techniques and makes use of the inherent characteristics of p-channel MOS transistors. The delay line provides unit gain with a dynamic range of 1 volt. The bandwidth of the delay line is 0.8 MHz under nonsampling conditions. The lowest sampling rate was found to be 50 Hz. A built-in capacitive compensation technique using signals opposite in phase reduces feedthrough of the sampling signal and final filtering requirements. Investigation of the problems of obtaining unity gain and dynamic range led to the development of a computer-aided analysis that provides a family of dc transfer characteristics of cascaded p- channel MOS `half-stages' when a variation of either a material or electrical parameter is made.