Abstract
We present the development of a device-level linearization technique and its applications in broadband power amplifiers (PAs). The proposed topology firstly combines derivative transconductance superposition method and gate capacitance compensation technique, and creates a "sweet region" for suppressing third-order intermodulation (IM3) without the penalty of large power consumption. The effectiveness of the proposed technique has been demonstrated through a fully integrated distributed amplifier. The experimental results in 0.18-mum RF CMOS technology show that IM3 is improved by 11 dB. The achievable power-added efficiency is up to 25%, which is the highest among the broadband CMOS PAs reported thus far. The amplifier achieves a measured 3-dB bandwidth of 3.7-8.8 GHz, and a gain of 8.24 dB. The amplifier only consumes 154-mW dc power, and the measured saturation power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) is 19 dBm.
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