In this paper, an alternative approach for the extraction of effective channel length, Leff, using a modified capacitance–voltage (C–V) method [the capacitance–ratio (C–R) method], which considers depletion effect compensation is proposed. In general, we define Leff=Lmask-ΔL, where ΔL is the sum of the polysilicon gate lithography bias and two times the overlap length of the polysilicon gate and source/drain (S/D) extension (ΔL=Lpb+2Lovlap). Using the modified C–V method, more consistent and reasonable Leff data can be extracted as compared to those obtained using the newest current–voltage (I–V) method (shift and ratio method). In using the proposed C–R method, we can electrically measure the exact Lpb and Lovlap numbers that can both be used as process monitor parameters. The within-wafer uniformities of Leff (or ΔL), Lpb and Lovlap have also been checked among devices of various sizes. After the Leff is extracted, a stable S/D resistance Rsd, with Vg independence, is determined and verified using the I–V method. The parasitic capacitance Cgd is another extracted parameter that is as important as Rsd in SPICE modeling for RF complementary metal-oxide-semiconductor (CMOS) applications.