Capacitance Standards Research Articles

New proposed method for traceability dissemination of capacitance measurements

Capacitance measurements at the National Institute of Standards (NIS), Egypt, are traceable to the Bureau International des Poids et Mesures (BIPM). It calibrates the main NIS standard capacitors, AH11A. In this paper, traceability of the BIPM capacitance measurements could be used to evaluate a new accurate measurement method through an Ultra-Precision Capacitance Bridge. The new method is carefully described by introducing some necessary equations and a demonstrating chart. Verification of this new method has been realized by comparing its results for the 10 pF and 100 pF capacitance standards with the results obtained by the conventional substitution method at 1 kHz and 1.592 kHz. The relative differences between the two methods are about 0.3 µF/F, which reflect the accuracy of the new measurement method. For higher capacitance ranges, the new measurement method has been applied for the capacitance measurements up to 1 μF at 1 kHz. The relative differences between the two methods are in the range of 5.5 µF/F on the average which proves the acceptable accuracy and the reliability of the new method to be used.

A four-terminal-pair Josephson impedance bridge combined with a graphene-quantized Hall resistance

This paper introduces a four-terminal-pair impedance bridge based on pulse-driven Josephson junctions arrays which is designed to link any kind of impedance to the quantized Hall resistance. The unique features of the quantized Hall resistance in a multiple series connection allows to dispense a combining network and leads to a compact and simple design of the whole setup. Moreover, the low noise of a quantized Hall resistance reduces the measurement time compared to resistance standards at room temperature which is essential for the characterization of quantum Hall devices in the AC regime. A first measurement campaign confirmed the expected low noise of 1.82 for a link to a 10 nF capacitance standard. The repeatability of the bridge was found to be few parts in 108. Capacitance and resistance standards were measured at 1233.15 Hz against graphene based quantum Hall resistance devices.

SMOOTHING OF THE INTERMITTENT POWER PROVIDED BY WAVE POWER PLANTS USING ULTRACAPACITORS AND A NON-LINEAR VECTOR CURRENT CONTROLLED MMC

This article focuses on smoothing the large power peaks that wave energy converters (WECs) inject into the electrical grid. The study is carried out for a single WEC where the generated power is delivered to the grid by means of a power converter. Two different measures have been considered to improve the power quality of the grid connection. Firstly, the electronic converter has been chosen a modular multilevel converter (MMC) to allow replacing the standard high voltage capacitors of the DC link by low voltage ultracapacitors distributed across the modules of the MMC. Secondly, the MMC is controlled using a non-linear vector current control. The results show that the power delivered to the grid becomes approximately constant when using ultracapacitors. Furthermore, the non-linear vector current source provides the grid connection converter with the necessary fast dynamic response to avoid large variations in the DC voltage. Keywords: modular multilevel converter (MMC); non-linear vector current source; ultracapacitor; wave energy converter (WEC).

Parasitic Capacitance Analysis of Three-Independent-Gate Field-Effect Transistors

Three-Independent-Gate Field-Effect Transistors (TIGFETs) are a promising alternative technology that aims to replace or complement CMOS at advanced technology nodes. In this paper, we extracted the parasitic and intrinsic capacitances of a silicon-nanowire TIGFET device using three-dimensional numerical simulations in an attempt to accurately compare its capacitances and, consequently, circuit-level performances to CMOS at comparable nodes. Analytical models of the parasitic capacitances of a TIGFET transistor were derived using techniques such as the equivalent Schwarz-Christoffel transformation and standard cylindrical capacitors and show close agreement with numerical simulations. The maximum capacitance of a TIGFET transistor is $2\times $ larger than for a 15 nm CMOS High Performance (HP) device due to the TIGFET’s two additional gated contacts, but this is countered by its ability for multiple modes of operation which reduces the effective switching capacitance per device. A TIGFET transistor sees, on average, only a 30% increase in total capacitance compared to a CMOS HP device. Additionally, the TIGFET’s increased device functionality can be used to modify the circuit-level architecture of a TIGFET-based design to mitigate the performance impact of its larger device-level capacitance. This combination of a TIGFET’s (1) multiple modes of operation, and (2) circuit-level architecture lead to enhanced system performance. In particular, we show that at the 15 nm technology node TIGFET technology has 18% lower energy-delay product for a fan-out of 4 and higher when using 1-bit full-adder logic circuit than for the equivalent node CMOS HP.

A fully digital bridge towards the realization of the farad from the quantum Hall effect

This paper presents the implementation of an electronic fully-digital impedance bridge optimized for RC comparisons with equal impedance magnitudes, together with an evaluation of the uncertainty. This bridge has been designed with the goal of realizing the farad directly from the quantum Hall effect with a bridge uncertainty component at the 10−7 level. Thanks to its simple design, ease of operation and affordability, this bridge is suitable to be industrially manufactured. Together with the increasing availability of graphene quantum Hall resistance standards, this can provide an affordable quantum realization of the unit farad for metrology institutes and calibration centres.In this paper we present the uncertainty budget of an example measurement and the results of the validation of the bridge against a suitably modified version of the traceability chain of the Italian national standard of capacitance. The combined uncertainty of the bridge resulted from repeated measurements (overall measurement time of about 200 min) is 9.2 × 10−8, suitable for the primary realization of the unit of capacitance from a quantized Hall resistance standard. The crosstalk among the channels of the electrical generator is the most significant uncertainty component, possibly reducible with internal shielding and filtering of the electronic generator.

A high-efficiency charge pump with charge recycling scheme and finger boost capacitor

A 16-phase 8-branch charge pump with finger boost capacitor is proposed to increase the power efficiency and it is implemented in a 0.35 μm high-voltage CMOS IC technology. Compared with the standard capacitor, the finger capacitor can significantly reduce the parasitic capacitance. By combining the charge recycling method and the finger capacitor, the proposed four-stage charge pump can achieve an efficiency of 47.2% and an output voltage of 13.7 V from a 3 V power supply. The proposed charge pump also has better current driving ability and the area of the chip is 2.32 mm × 0.28 mm.

A substitution method for nanoscale capacitance calibration using scanning microwave microscopy

This paper presents a calibration method and an uncertainty budget for capacitance measurements performed on micrometric size capacitors at microwave frequencies and nanometric resolution using a scanning microwave microscopy (SMM). The method applies the classical one-port vector network analyzer calibration for SMM using three known capacitance standards. These standards are established from a commercial calibration kit placed close to the microcapacitors in order to be calibrated. The calibration kit is composed of a large number of Metal-Oxide-Semiconductor (MOS) microcapacitors with capacitance values C ranging from 0.1 fF to 8.6 fF. Diligent selection criteria were established for the choice of the three capacitors. Their capacitance values were calculated from the AFM measured values of the area of the top electrodes and the dielectric thickness and considering the contribution of fringing fields. The combined type uncertainty on these calculated values amounts between 5% and 14% in relative value (uncertainty given at one standard deviation). The comparison between the capacitance values measured on calibration kit capacitors using the calibrated SMM and the calculated values show a good agreement for capacitances higher than 0.8 fF within uncertainties varying between 6% and 9%. For smaller capacitances, most of the observed deviations are not significant at two standard deviations. The uncertainties are mostly dominated by dimensional measurements and less importantly by unwanted capacitance effects. Based on these results, capacitances of two sets of microcapacitors were calibrated. The combined uncertainties vary from 14% to 7% for capacitances ranging from 0.1 fF to 3.1 fF respectively. The permittivity values of the dielectric layer of the two samples have been determined. They are found equal to 4.0 and 4.1 with a standard uncertainty of 0.6 and correlate with the expected value of 3.9.

The Research on Additional Errors of Voltage Transformer Connected in Series

The series summation method is an important method in the calibration of the voltage coefficient (VC) of the standard voltage transformers (VTs), in which the key step is connecting a fullyinsulated VT and a semi-insulated VT in series, and comparing them with the third VT under test. Caused by the imperfect electrical shielding of the serially-wound VTs, additional errors are introduced in the calibration. By analyzing the cause of the additional errors in the serial connection of the VTs, two methods were designed in this paper to measure the additional errors. The proposed methods were harnessed to measure the additional errors for a serial connection of a 35 kV fully-insulated two-stage voltage transformer (TSVT) and a 35 kV semi-insulated TSVT. The results show that the two methods give a consistency of better than 1.0 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> in ratio error and 2.0 μrad in phase displacement, respectively. The accurate measurement of the series additional errors and the correction of them significantly improve the accuracy of the VC measurement of a 110/√3 kV TSVT based on the series summation method. Furthermore, the VC measurement result is verified by the consistency of the series summation method with the series additional errors corrected and the high-voltage standard capacitor method.

Monitoring of AH-11A fused-silica drift in RCM-LIPI and its implementation

We have been monitoring our standard capacitors of AH-1100 fused-silica drift for 8 years to maintain and obtain the actual values of them. One of the advantages of the standard capacitors is to be used as a reference standard for ensuring the performance of an AC high voltage capacitive divider, that is commonly used to assess a voltage level on a power distribution from plants to end-users. This paper describes the monitoring of AH-1100 and its validation performed by comparing to the calibration results of KRISS, the national metrology institute of The Republic of Korea. The AH-1100 drifts is found to be less than 0.0052μF/F/year, and the comparison results show a good agreement, making the monitoring results have been validated. Moreover, the implementation has been performed with expanded uncertainties of 1.7 fF for 10 pF and about 22 fF for 100 pF.

Electrofabricated biomaterial-based capacitor on nanoporous gold for enhanced redox amplification

Redox reactions are widely utilized as a transduction modality for biological to electrical communication. Biomaterial-based redox capacitors are emerging as a promising bio-device interface, since the redox-cycling current from interaction of a pair of mediators with the redox capacitor film can be amplified when the redox potentials of the mediators bracket that of the capacitor. We present a method to further amplify the signal responses of a standard catechol-chitosan redox capacitor by carrying out the electrofabrication and electrochemical signal measurements on nanoporous gold (NPG) patterned in a microfluidic channel. Specifically, a pH-responsive chitosan film is electrodeposited on an NPG covered gold electrode, which is electrochemically grafted with catecholic species and modified by a self-assembled monolayer of mercapto-hexanol to enable electrochemical measurements under ambient conditions. The resulting nanoporous architecture of the “NPG/redox-capacitor” enhances the spatial extent across the film depth that is available to the redox mediator for electron transfer interactions with the electrode before escape into the bulk film, thereby enabling significantly higher capacity versus that obtained on a conventional redox capacitor. The sensitivity and biocompatibility of this NPG/redox-capacitor are validated on a micro-device platform by demonstrating its ability to quantitatively detect the redox active bacterial metabolite: pyocyanin, directly from growth cultures of the opportunistic pathogen: Pseudomonas aeruginosa. Due to the capability for microfluidic integration, we envision that this NPG/redox-capacitor electrofabrication strategy can widely impact studies on biological to electrical communication.

Reference Ultralow DC Current Source Between 1 fA and 100 pA at TÜBİTAK UME

In this paper, we present a programmable Ultra Low DC Current Source (ULCS) developed at T\"UB\.ITAK UME. The output current range is from 1 fA up to 100 pA with 100 aA resolution and is directly traceable to DC voltage, capacitance and time units. The principle of the device is based on applying a linear ramp voltage on standard capacitors with values between 1 pF and 1000 pF. These standard capacitors are commercial standard capacitors which are kept in a temperature controlled insulated box. Linear ramp voltage is generated using a commercial DAQ card. Current source device is fully automated with computer control and can be used to generate any currents with 100 aA resolution in its full range. The uncertainty is 2.5 mA/A at 1 fA current.

Role of Quasiparticles in an Electric Circuit with Josephson Junctions.

Although Josephson junctions can be viewed as highly nonlinear impedances for superconducting quantum technologies, they also possess internal dynamics that may strongly affect their behavior. Here, we construct a computational framework that includes a microscopic description of the junction (full fledged treatment of both the superconducting condensate and the quasiparticles) in the presence of a surrounding electrical circuit. Our approach generalizes the standard resistor capacitor Josephson model to arbitrary junctions (including, e.g., multiterminal geometries and/or junctions that embed topological or magnetic elements) and arbitrary electric circuits treated at the classical level. By treating the superconducting condensate and quasiparticles on equal footings, we capture nonequilibrium phenomena such as multiple Andreev reflection. We show that the interplay between the quasiparticle dynamics and the electrical environment leads to the emergence of new phenomena. In a RC circuit connected to single channel Josephson junction, we find out-of-equilibrium current-phase relations that are strongly distorted with respect to the (almost sinusoidal) equilibrium one, revealing the presence of the high harmonic ac Josephson effect. In an RLC circuit connected to a junction, we find that the shape of the resonance is strongly modified by the quasiparticle dynamics: close to resonance, the current can be smaller than without the resonator. Our approach provides a route for the quantitative modeling of superconducting-based circuits.

A high-efficiency and compact charge pump with charge recycling scheme and finger boost capacitor

A 16-phase 8-branch charge pump with finger boost capacitor is proposed to increase the power efficiency. Compared with the standard capacitor, the finger capacitor can significantly reduce the parasitic capacitance. The proposed four-stage charge pump with finger capacitor can achieve 14.2 V output voltage from a 3 V power supply. The finger capacitor can increase the power efficiency of the charge pump to 60.5% and save chip area as well.

Modified method of identification of mutual fractional-order inductance

The paper presents a method for identifying the parameters Mγ, γ of a fractional-order transformer, which parameters Lβ1, β1, Lβ2, β2 have been previously determined. This method is based on the measurement of the phase resonance frequency in a few systems containing: the investigated fractional-order transformer and two standard capacitors. The measurements need to be performed only for one series opposite-aiding connection of the fractional-order transformer. The dependencies allowing the determination of the fractional-order mutual inductance parameters have been given

Bilateral comparison of 10 pF and 100 pF standards (ongoing BIPM key comparisons BIPM.EM-K14.a and 14.b) between the NIMT (Thailand) and the BIPM

This report presents the results of a bilateral comparison of 10 pF and 100 pF capacitance standards between the NIMT (Thailand) and the BIPM carried out in 2018. The comparison at 10 pF forms part of the ongoing BIPM key comparison BIPM.EM-K14.a and that at 100 pF of the ongoing BIPM key comparison BIPM.EM-K14.b. The BIPM is the pilot laboratory for both of these comparisons.Two 10 pF and one 100 pF travelling standards belonging to the NIMT were used in this comparison carried out with an 'A-B-A' pattern of measurements. The standards were measured first at NIMT for a period of about one month, then for a similar period at the BIPM, and finally again at NIMT. The measurand was the two terminal-pair capacitance at a frequency of either 1000 Hz or 1592 Hz, for a measuring rms voltage of 15 V at 10 pF and 10 V at 100 pF.The results from the NIMT and the BIPM at both 1000 Hz and 1592 Hz were found to be in good agreement, with a difference smaller than the relative expanded uncertainty of the comparison.Main textTo reach the main text of this paper, click on Final Report. Note that this text is that which appears in Appendix B of the BIPM key comparison database kcdb.bipm.org/.The final report has been peer-reviewed and approved for publication by the CCEM, according to the provisions of the CIPM Mutual Recognition Arrangement (CIPM MRA).

Comparison CCEM-K4.2017 of 10 pF and 100 pF capacitance standards

In 2017 the Consultative Committee for Electricity and Magnetism (CCEM) commissioned a key comparison of electrical capacitance standards, the second time this quantity has been compared since the implementation of the Mutual Recognition Agreement by the Comité International des Poids et Mesures (CIPM—MRA) in 1999. This comparison—CCEM-K4.2017—was piloted by the Bureau International des Poids et Mesures (BIPM) and included seven National Metrology Institutes (NMI) belonging to four Regional Metrology Organizations.The measuring scheme adopted for the comparison was that of a star comparison consisting of a set of bilateral comparisons between the participating NMIs and the BIPM, whose capacitance reference base served as a common reference. For each of the bilateral comparisons, the measurands were the capacitance values of 10 pF travelling standard capacitors belonging to the NMIs and, optionally, the values of 100 pF standards.All the participants have been chosen from those able to realize and maintain a representation of the farad at the best known level of accuracy. Four of them, including the BIPM, were taking their traceability from dc or ac quantum Hall effect standards and, the four others, from a calculable capacitor.The comparison results analysis have evidenced an agreement within about ±5 parts in 108 for the mandatory 10 pF measurements and within about ±10 parts in 108 for the optional 100 pF measurements. Also, excepted for one of the participants, a good agreement has been found for the ratio 100 pF:10 pF (within ±5 parts in 108).In addition to the comparison, it has been possible to evaluate the difference between the value of R K (von Klitzing constant) measured by electrical means from calculable capacitors and its last CODATA recommended value (CODATA 2014 adjustment). A difference of (43 ± 23) parts in 109 (k = 1) has been found which is consistent with the difference that can be computed from the experimental data used in the CODATA 2014 adjustment of fundamental constants.This report presents the details of the measurements and analysis having led to these results.Main textTo reach the main text of this paper, click on Final Report. Note that this text is that which appears in Appendix B of the BIPM key comparison database kcdb.bipm.org/.The final report has been peer-reviewed and approved for publication by the CCEM, according to the provisions of the CIPM Mutual Recognition Arrangement (CIPM MRA).

Impedance bridges: from Wheatstone to Josephson

This paper reviews the recent evolution of the measurement techniques in the area of impedance measurement from the Wheatstone bridge to the most advanced Josephson-based digital impedance bridge. The progress in the development of high sampling rate, high accuracy digital-to-analog and analog-to-digital converters has led to the development of digital impedance bridges that have profoundly modified the landscape of impedance metrology. Although these new bridges do not yet outperform the traditional transformer-based bridge in terms of accuracy, they significantly improve their measurement capabilities and flexibility by allowing a complete automation, a full coverage of the complex plane, arbitrary bridge ratios and extended frequency range. In addition, after the redefinition of the International System of Unit, they will contribute to the realization of the henry and the farad by establishing a direct link between the quantized Hall resistance and the capacitance or inductance standards.

Molecular dynamics modeling framework for overcoming nanoshape retention limits of imprint lithography

Complex nanoshaped structures (nanoshape structures here are defined as shapes enabled by sharp corners with radius of curvature <5 nm) have been shown to enable emerging nanoscale applications in energy, electronics, optics, and medicine. This nanoshaped fabrication at high throughput is well beyond the capabilities of advanced optical lithography. While the highest-resolution e-beam processes (Gaussian beam tools with non-chemically amplified resists) can achieve <5 nm resolution, this is only available at very low throughputs. Large-area e-beam processes, needed for photomasks and imprint templates, are limited to ~18 nm half-pitch lines and spaces and ~20 nm half-pitch hole patterns. Using nanoimprint lithography, we have previously demonstrated the ability to fabricate precise diamond-like nanoshapes with ~3 nm radius corners over large areas. An exemplary shaped silicon nanowire ultracapacitor device was fabricated with these nanoshaped structures, wherein the half-pitch was 100 nm. The device significantly exceeded standard nanowire capacitor performance (by 90%) due to relative increase in surface area per unit projected area, enabled by the nanoshape. Going beyond the previous work, in this paper we explore the scaling of these nanoshaped structures to 10 nm half-pitch and below. At these scales a new “shape retention” resolution limit is observed due to polymer relaxation in imprint resists, which cannot be predicted with a linear elastic continuum model. An all-atom molecular dynamics model of the nanoshape structure was developed here to study this shape retention phenomenon and accurately predict the polymer relaxation. The atomistic framework is an essential modeling and design tool to extend the capability of imprint lithography to sub-10 nm nanoshapes. This framework has been used here to propose process refinements that maximize shape retention, and design template assist features (design for nanoshape retention) to achieve targeted nanoshapes.

An accurate on-site calibration system for electronic voltage transformers using a standard capacitor

Ordinarily electronic voltage transformers (EVTs) are calibrated off-line and the calibration procedure requires complex switching operations, which will influence the reliability of the power grid and induce large economic losses. To overcome this problem, this paper investigates a 110 kV on-site calibration system for EVTs, including a standard channel, a calibrated channel and a PC equipped with the LabView environment. The standard channel employs a standard capacitor and an analogue integrating circuit to reconstruct the primary voltage signal. Moreover, an adaptive full-phase discrete Fourier transform (DFT) algorithm is proposed to extract electrical parameters. The algorithm involves the process of extracting the frequency of the grid, adjusting the operation points, and calculating the results using DFT. In addition, an insulated automatic lifting device is designed to realize the live connection of the standard capacitor, which is driven by a wireless remote controller. A performance test of the capacitor verifies the accurateness of the standard capacitor. A system calibration test shows that the system ratio error is less than 0.04% and the phase error is below 2′, which meets the requirement of the 0.2 accuracy class. Finally, the developed calibration system was used in a substation, and the field test data validates the availability of the system.

Design of an HV capacitor using the inherent advantage of charge simulation method and experimentations

Standard capacitors form an important component of the measurement and instrumentation in the electrical laboratory. A high-voltage (HV) standard capacitor of 100 pF, 12 kV (rms) is designed using the charge simulation method (CSM). CSM is a semi-analytical method and it provides inherent advantage in designing a capacitor from the first principle. The capacitance is obtained from the magnitude of the simulating charges of the CSM-based model and the corresponding potential. The design details of HV standard capacitor are discussed along with the analysis of the potential and the electric stress distribution. The electric stress everywhere in the capacitor, which is designed, is assured to be <5 kV/cm, which was set as the limiting (maximum permissible) stress. The capacitance of the fabricated unit is measured in the HV laboratory. The CSM-based result of the capacitance of the designed HV capacitor agree well with the results of the laboratory experimental measurement. The inherent advantage of CSM in designing a capacitor is confirmed by comparing with the results of method of moments (MoM).