Capacitance Ratio Research Articles

Design and Fabrication of a Ka Band RF MEMS Switch with High Capacitance Ratio and Low Actuation Voltage.

In this paper a high capacitance ratio and low actuation voltage RF MEMS switch is designed and fabricated for Ka band RF front-ends application. The metal-insulator-metal (MIM) capacitors is employed on a signal line to improve the capacitance ratio, which will not degrade the switch reliability. To reduce the actuation voltage, a low spring constant bending folding beam and bilateral drop-down electrodes are designed in the MEMS switch. The paper analyzes the switch pull-in model and deduces the elastic coefficient calculation equation, which is consistent with the simulation results. The measured results indicated that, for the proposed MEMS switch with a gap of 2 μm, the insertion loss is better than −0.5 dB and the isolation is more than −20 dB from 25 to 35 GHz with an actuation voltage of 15.8 V. From the fitted results, the up-state capacitance is 6.5 fF, down-state capacitance is 4.3 pF, and capacitance ratios is 162. Compared with traditional MEMS capacitive switches with dielectric material Si3N4, the proposed MEMS switch exhibits high on/off capacitance ratios of 162 and low actuation voltage.

Vertical‐Pillar Ferroelectric Field‐Effect‐Transistor Memory

In recent years, following trends in developing semiconductors, extensive research has been conducted to develop a hafnia‐based ferroelectric field effect transistor (FeFET) memory. However, its fundamental endurance limitation, which stems from early degradation of the gate insulator, has been a major obstacle to the development of FeFETs, with no clear solution despite attempting various approaches to high‐speed and high‐reliability FeFETs. Herein, a novel metal–ferroelectric–metal–insulator–semiconductor FeFET with vertical‐pillar channel and metal–ferroelectric–metal capacitor (VP‐FeFET) that can adjust the capacitance ratio between the ferroelectric film and gate insulator by modulating the channel height is proposed. The optimized VP‐FeFET exhibits a significantly reduced electric field (≤1.5 MV cm−1) through the gate insulator, resulting in a substantially enhanced FeFET endurance. Furthermore, the proposed FeFET achieved a large memory window of ≈5 V and a high program/erase speed of ≈100 ns. These merits are achieved without increasing the footprint of the FeFET device. This approach to high‐performance FeFET can be applied extensively to next‐generation nonvolatile memory devices.

Influence of shunt capacitance on impact load measurement of polyvinylidene fluoride sensor

Shunt capacitance is one of the most critical parts of the test circuit in charge mode, and its influence on impact load measurement of polyvinylidene fluoride (PVDF) is worth discussing. In this study, several experiments are conducted by connecting different shunt capacitances. The results show that in addition to the shunt capacitor, the charge generated is partially concentrated on the PVDF capacitor and extra capacitor, and the amount depends on the capacitance ratio. The source of the extra capacitance is the test circuit parasitic capacitance and the PVDF capacitance change during the impact load, and their influence must be minimized due to difficulty to measure or calculate. Therefore, based on the measurement principles, the interference caused by the extra capacitance in the charge and current modes is analyzed, and suitable measurement conditions are compared. Research in this paper is helpful to improve the accuracy of impact load measurement with PVDF.

Complementary Metal–Oxide–Semiconductor Compatible 2D Layered Film‐Based Gas Sensors by Floating‐Gate Coupling Effect

AbstractA 2D SnSe2 layered film‐based gas detector incorporating a floating‐gate device coupled with metal interconnect wiring structures is proposed and demonstrated for the first time. Linear amplification can be readily implemented using a coupling ratio design, which refers to the capacitance ratio between the gate and device in the sense amplifier circuits. A sensitivity of 102 mV ppm−1 can be obtained using the 2D SnSe2 layered film with a thickness of 10 nm. The 2D SnSe2 layered film‐based complementary metal–oxide–semiconductor (CMOS) gas detector features highly sensitive, wide, and adjustable dynamic ranges with a real‐time response of the sub‐ppm detection limit on NO2 gas. In addition, the synthesis process of the SnSe2 layered film can occur at a low temperature and be operated at room temperature. Furthermore, 3 × 3 gas detector arrays with peripheral circuits demonstrate the functionality of multiple gas detection simultaneously and 16 × 16 arrays with a decoder and other peripheral circuits are constructed and simulated, providing the spatial distribution of the gas concentration in a specific region. The performance of the proposed detector is comparable to that of the other state‐of‐the‐art gas sensors.

High-performance inline RF MEMS switch for application in 5G mobile networks

This article presents the results of the design and analysis of a radio-frequency switch made using microelectromechanical systems technology. The device is the capacitive switch with a hybrid type of contact, in which the movable electrode of the structure – the metal membrane is part of the microwave signal line of the coplanar waveguide. The switch design is characterized by a high capacitance ratio and low contact resistance. The zig-zag elastic suspension is used to reduce the value of the pull-down voltage – 2 V and the switching time ∼ 7 us. The central resonant frequency of the switch is 3.8 GHz. In this case, in the open state, the value of the insertion loss is not more than -0.2 dB and the isolation value in the close state is not less than -55 dB. The effective frequency range is the S-band, as well as the C-, X- and Ku-band, in which the isolation value is at least -30 dB. The presented inline RF MEMS switch is suitable for use in various types of ground and satellite communications, in particular for devices and systems of 5G mobile networks.

RESEARCH OF METHODS FOR DECREASE OF THE CAPACITANCE RATIO IN THE STW-RESONATORS

This paper presents the research of methods for decrease of the capacitance ratio in the STW-resonators without significant degradation of the quality factor by use of the external inductors and topology change: IDT division on parts and their series connection. The calculated and experimental data are presented for 416 MHz and 766 MHz STW-resonators with quality factors Q = 7000–7978. The capacitance ratio has been reduced from 1200 to 301.

A Comparative Performance Analysis of Zero Voltage Switching Class E and Selected Enhanced Class E Inverters

This paper presents a comparative analysis of the class E and selected enhanced class E inverters, namely, the second and third harmonic group of class EFn, E/Fn and the class E Flat Top inverter. The inverters are designed under identical specifications and evaluated against the variation of switching frequency (f), duty ratio (D), capacitance ratio (k), and the load resistance (RL). To offer a comparative understanding, the performance parameters, namely, the power output capability, efficiency, peak switch voltage and current, peak resonant capacitor voltages, and the peak current in the lumped network, are determined quantitatively. It is found that the class EF2 and E/F3 inverters, in general, have higher efficiency and comparable power output capability with respect to the class E inverter. More specifically, the class EF2 (parallel LC and in series to the load network) and E/F3 (parallel LC and in series to the load network) maintain 90% efficiency compared to 80% for class E inverter at the optimum operating condition. Furthermore, the peak switch voltage and current in these inverters are on average 20–30% lower than the class E and other versions for k > 1. The analysis also shows that the class EF2 and E/F3 inverters should be operated in the stretch of 1 < k < 5 and D = 0.3–0.6 at the optimum load to sustain the high-performance standard.

Tuning of subwavelength topological interface states in locally resonant metastructures with shunted piezoelectric patches

We investigate the propagation behavior of the low-frequency topological interface state of the flexural wave in the locally resonant metastructure and analyze the tunability of the sub-wavelength interface states by the piezoelectric shunting circuit. One homogeneous thin beam is periodically attached with local resonant beams, which connect shunted piezoelectric actuators. The folding band obtained by merging two primitive unit cells into one new element can generate a Dirac point below the low-frequency locally resonant bandgap. This folding point is opened to develop one new bandgap originated from the Bragg scattering effect by breaking the mirror symmetry. Then, topological transitions are demonstrated during the distance variation between two adjacent resonances. The interface state’s existence is further confirmed by using steady and transient analysis of the heterostructure composed of two media with different topological properties. Finally, we show the relationship between the interface frequency and the capacitance ratio and research the influence of the distance parameter on the topological interface state. Because of the tunability of elastic waves by the piezoelectric shunting circuit, our design has potential for applications such as energy harvesters, filters, and physical switches.

Indoor Comfort Achieved Exclusively From Ambient Sources Across US Climates

Abstract This study tests the feasibility of a more climate-friendly approach to space conditioning. This new strategy (called Ambient House) employs thermal mass in conjunction with ambient sources of heat and cold to maintain indoor temperature within a comfortable range with no auxiliary energy. Buildings in 11 US climate zones were simulated as first-order systems with envelope losses, internal heat gains, solar gains, and heat rejection by natural ventilation. Building similitude parameters were adjusted to maintain indoor temperature within a range of 20–25 °C. Building performance is defined by two mathematical parameters. First, the asymptotic temperature difference, which is a ratio of solar and internal heat gains to envelope losses and ventilation cooling, also incorporates control functions for solar heating and ventilation cooling. Second, the building time constant is the ratio of thermal capacitance to envelope losses and ventilation cooling. Temperature response was compared with that of buildings with the same characteristics, except low thermal mass. Without auxiliary heating and cooling and without active controls, low mass buildings reached temperatures as low as −3 °C and over 70 °C. With controls, extreme temperatures were still −3 to 40 °C. The Ambient House comfort temperature range was achievable with thermal mass within or near that of conventional construction in all but the hot climates of Miami, New Orleans and Phoenix. In these locations, large thermal mass and high ventilation cooling were required. This study confirms that it is feasible to thermally condition spaces exclusively with ambient sources in all the US climate zones.

Silicene Quantum Capacitance Dependent Frequency Readout to a Label-Free Detection of DNA Hybridization- A Simulation Analysis.

The use of deoxyribonucleic acid (DNA) hybridization to detect disease-related gene expression is a valuable diagnostic tool. An ion-sensitive field-effect transistor (ISFET) with a graphene layer has been utilized for detecting DNA hybridization. Silicene is a two-dimensional silicon allotrope with structural properties similar to graphene. Thus, it has recently experienced intensive scientific research interest due to its unique electrical, mechanical, and sensing characteristics. In this paper, we proposed an ISFET structure with silicene and electrolyte layers for the label-free detection of DNA hybridization. When DNA hybridization occurs, it changes the ion concentration in the surface layer of the silicene and the pH level of the electrolyte solution. The process also changes the quantum capacitance of the silicene layer and the electrical properties of the ISFET device. The quantum capacitance and the corresponding resonant frequency readout of the silicene and graphene are compared. The performance evaluation found that the changes in quantum capacitance, resonant frequency, and tuning ratio indicate that the sensitivity of silicene is much more effective than graphene.

Photo-dielectric response enhancement and switching behavior of (1-x)(K0.5Na0.5)NbO3-xCa(Ni0.5Nb0.5)O3-δ ceramics by semiconduction method

The lead-free ferroelectric ceramics with high photo-dielectric response will contribute to developing new contactless photoelectric devices. The (1-x)(K0.5Na0.5)NbO3-xCa(Ni0.5Nb0.5)O3-δ (KNN-xCNN) ferroelectric semiconductive ceramics prepared by solid-phase sintering were used to investigate photo-dielectric behavior. After introducing the CNN component, the hysteresis loops of KNN-xCNN ceramics changed from the normal P-E loops to the pinched P-E loops, and the relaxation behavior was enhanced by the increase of diffusion coefficient from 1.16 to 1.85. The phase structure transformed from the orthogonal phase to the tetragonal phase. The grain size decreasing from 360 nm to 170 nm was refined. The bandgap decreased significantly from 2.29 eV to 1.40 eV. An obvious enhanced photo-dielectric response was achieved under ultraviolet light irradiation, which shows high dielectric tunability of ~387% at x = 0.015. Meanwhile, the switching behavior was analyzed by the capacitive ratio under light on and off state, which is about 5. These results pave the way for new photoelectric coupling devices such as photo-adjustable capacitor and capacitive switching.

Tuning the microstructures of uniform carbon spheres by controlling the annealing conditions for high-performance lithium-ion full batteries and lithium-ion capacitors

Microstructures include graphited microcrystal structures, micro-pores, specific areas, and pore volume of hard carbon spheres (CSs), have been tuned to optimize their Li+ storage performance by annealing at different temperature. The sample annealed at 650 °C (CS-650) exhibits the best performance for Li+ storage with high specific capacity, stable cycling stability, and superior rate performance. The CS-650 displays an initial capacity of 284 mAh g–1 at a specific current of 0.3 A g–1 with 277 mAh g–1 can be retained after 400 cycles, and a specific capacity of 180 mAh g–1 can be achieved at a high specific current of 2.0 A g–1. More significantly, the CS-650 exhibits a high capacitive contribution ratio from 62.2% to 76.0% as the scan rate increases from 0.3 to 1.0 mV s−1 due to its high specific area and large pore volume. The capacitive behaviour of CS-650 enhances the reaction kinetics for high energy and high-power applications in both full battery and Li-ion capacitor (LIC), which are assembled with LiNi0.5Co0.2Mn0.3O2 cathode and activated carbon positive electrode, respectively. The CS-650-based full battery shows a specific capacity of 66.1 mAh g−1 at 0.1 A g−1 combined with high cycling stability. The LIC displays a specific energy of 115 Wh kg−1 at 242 W kg−1 with a specific energy of 48 Wh kg−1 at 2364 W kg−1. Our work indicates that the Li+ storage performance of hard carbon can be tuned by the microstructure and both high energy and high power performances can be achieved.

Emerging Fluorite‐ and Wurtzite‐Type Ferroelectrics: From (Hf,Zr)O2 to AlN and Related Materials

Emerging Fluorite‐ and Wurtzite‐Type Ferroelectrics: From (Hf,Zr)O₂ to AlN and Related Materials

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of -247dB, and normalized TR and area (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TA</sub> ) of -262dB.

High‐Performance and High‐Endurance HfO2‐Based Ferroelectric Field‐Effect Transistor Memory with a Spherical Recess Channel

Owing to their high scalability and superior complementary metal–oxide–semiconductor (CMOS) compatibility, HfO2‐based ferroelectric field‐effect transistors (FeFETs) are proved to be promising candidates for emerging nonvolatile memory devices. However, the poor endurance of these FeFETs, which is attributed to the degradation of the interfacial dielectric layer, is a serious obstacle for commercialization. In FeFETs with a metal–ferroelectric–insulator–semiconductor gate stack, the strong electric field across the interfacial dielectric layer mainly induces charge injection/trapping and limits endurance to &lt;106 cycles. Herein, optimum condition of switching polarization () of ferroelectric materials and a new structural approach to reduce the strength of the electric field across the interfacial dielectric layer and improve memory window (MW) and reliability properties are presented. Based on numerical simulation, it is found that an interfacial electric field increases with , and a metal–ferroelectric–metal–insulator–semiconductor FeFET with a 3D channel structure is effective to have high ratio of dielectric capacitance to ferroelectric capacitance, resulting in low electric field through the interfacial layer and large MW.

WS2 nanosheets@ZIF-67-derived N-doped carbon composite as sodium ion battery anode with superior rate capability

Devising novel composite electrodes with particular structural/electrochemical characteristics becomes an efficient strategy to advance the performance of rechargeable battery. Herein, considering the homogeneous transition metal sulfide with N-doped carbon derived from zeolitic imidazolate framework-67 (ZIF-67) and WS2 with large interlayer spacing, a laurel-leaf-like Co9S8/WS2@N-doped carbon bimetallic sulfide (Co9S8/WS2@NC) is engineered and prepared via a step-by-step method. As an electrode material for sodium ion batteries (SIBs), Co9S8/WS2@NC composite delivers high capacities of 480 and 405 mA h g−1 at 0.1 and 1.0 A g−1, respectively. As the current density increases from 0.1 to 5.0 A g−1, it provides specific capacity of 359 mA h g−1 with a capacity retention rate of 78.0%, which is higher than that of Co9S8@NC (63.5%) and WS2 (58.6%). The Co9S8/WS2@NC composite anode maintains a stable specific capacity (354 mA h g−1 at 2.0 A g−1). It also exhibits a high capacitive contribution ratio of 90.8% at 1.0 mV s−1. This study provides a new and reliable insight for designing bimetallic sulfide with two-dimensional nanostructure for energy storage.

Materials Selection Approaches and Fabrication Methods in RF MEMS Switches

A state of the art review on Radio Frequency Micro-Electromechanical Systems (RF MEMS) capacitive switches is reported by considering two key aspects: (1) materials selection approaches for improving performance, and (2) fabrication methods used in capacitive MEMS switches. The beam and dielectric materials used in capacitive MEMS switches and the performance achieved through them are reviewed and reported by a rigorous literature survey. Further, materials selection approaches for the beam membrane and the dielectric layer are discussed using Ashby’s methodology, and other associated methods based on it, which uses material indices to evaluate the performance of a switch. Performance indicators for the beam materials selection are the pull-in voltage, RF loss, thermal residual stress, contact resistance, thermal conductivity, and maximum displacement, whereas the hold-down voltage, dielectric charging, leakage current, heat dissipation, capacitance ratio, and stability are performance indicators in dielectric materials selection. MEMS switch fabrication can be achieved through bulk micromachining processes and surface micromachining processes, but the surface micromachining process has been preferred over the last few decades. The fabricated MEMS switch components can be integrated using a monolithic complementary metal oxide semiconductor–micro-electromechanical systems (CMOS-MEMS) process for the realization of applications in sensors, resonators, amplifiers, phase shifters, and MEMS satellite vehicles for space applications. CMOS-MEMS monolithic fabrication is discussed further with the help of fabrication process involved and the process technology. The TSMC-CMOS 0.35 $$\upmu \hbox {m}$$ technology is one of the leading technologies in CMOS-MEMS fabrication and is mainly used.

Low Pull-in-Voltage RF-MEMS Shunt Switch for 5G Millimeter Wave Applications

RF MEMS switches have been employed in many commercial and defense applications due to their high potentiality at microwave and millimeter wave frequencies. In this paper, an RF MEMS shunt switch is designed with perforations and without perforations and simulated using iterative meanders for millimeter wave 5G applications. The proposed iterative meander offers a low spring-constant of 0.68 N/m and reduces the pull-in-voltage upto 1.8 V. The proposed perforated switch design is more reliable which operates with less transition time of 11.2 µs with a quality factor of 1.69. The switch possesses high capacitance ratio of 63. During ON condition, the switch shows low insertion loss of − 0.24 dB at 41 GHz and high isolation of − 46.7 dB at 38 GHz. The performance of the switch is analyzed by simulating it using COMSOL Multiphysics 5.2v (FEM tool). The obtained simulation results shows close approximation with the theoretical results and the switch is efficiently used for 5G millimeter wave applications.

Analysis and Design Considerations for Achieving the Fundamental Limits of Phase Noise in mmWave Oscillators With On-Chip MEMS Resonator

Very small electromechanical coupling coefficient in micro-electromechanical systems (MEMS) or acoustic resonators is quite a concern for oscillator performance, specially at mmWave frequencies. This small coefficient is the manifestation of the small ratio of motional capacitance to static capacitance in the resonators. This work provides a general solution to overcome the problem of relatively high static capacitance at mmWave frequencies and presents analysis and design techniques for achieving extremely low phase noise and a very high figure-of-merit (FoM) in an on-chip MEMS resonator based mmWave oscillator. The proposed analysis and techniques are validated with design and simulation of a 30 GHz oscillator with MEMS resonator having quality factor of 10,000 in 14 nm GF technology. Post layout simulation results show that it achieves a phase noise of −132 dBc/Hz and FoM of 217 dBc/Hz at offset of 1 MHz.

A critical look at interpretation of electrochemical impedance spectra of sol-gel coated aluminium

A proper assignment of time constants is important for the correct interpretation of the electrochemical impedance spectra of coated substrates. In this work, several model aluminium samples with different anodic oxide thicknesses were prepared and characterised. The aluminium samples were coated by a hybrid sol-gel formulation and studied by electrochemical impedance spectroscopy (EIS) during immersion in NaCl solution. A hierarchical model containing three R-C elements adequately described the impedance spectra of the coated samples. The R-C elements described the properties of sol-gel coatings, aluminium oxide layers and corrosion process. The contribution of the aluminium oxide layer to impedance was unambiguously proven to be at middle frequencies on the spectra. Furthermore, the “real” capacitances of oxide layers were obtained from two capacitance–CPE equations and their applicability was scrutinized. The obtained results presented an opportunity to determine the adhesion behaviour of the sol-gel coatings to the oxide layers, which was studied by analysing the ratio of the oxide layer capacitance of the sol-gel coated samples to the capacitance of the uncoated ones. It was demonstrated that the exposed surface area of the oxide to the electrolyte was about 60–68% and was not changing during immersion. Based on these findings, a degradation model of the sol-gel coating on anodised aluminium was proposed.