A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS

Chao-Chieh Li,Min-Shueh Yuan,Tsung-Hsien Tsai,Tien-Chien Huang,Hung-Yi Kuo,Yu-Tso Lin,Chih-Hsien Chang,Chung-Ting Lu,Hsien-Yuan Liao,Augusto Ronchini Ximenes,Chia-Chun Liao,Robert Bogdan Staszewski

doi:10.1109/tcsi.2021.3059484

Abstract

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm 2 , this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm 2 ), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOM T ) of -247dB, and normalized TR and area (FOM TA ) of -262dB.

Highlights

F REQUENCY synthesizers are widely used in mainstream SoC applications, which range from RF wireless to wireline communications, such as high-speed SERDES ( [1])
We present an all-digital phase-locked loop (ADPLL) fabricated in 10-nm FinFET technology to achieve a good supply noise rejection, wide tuning range, and reasonable jitter performance within a very limited area for clock generation and wireline communications SoCs [20]
An ring oscillator (RO)-based phaselocked loop (PLL) usually requires a wide bandwidth and high power supply rejection (PSR) low drop-out (LDO) to decrease its high sensitivity to noise and perturbations on the power supply lines coupling from the rest of the SoC, especially switching digital circuitry

Summary

Introduction

F REQUENCY synthesizers are widely used in mainstream SoC applications, which range from RF wireless to wireline communications, such as high-speed SERDES ( [1]).

Objectives

Methods

Findings

Conclusion