Parasitic Capacitance Research Articles

Design of IPMSM Considering Shaft Voltage and AC Copper Loss for EV Propulsion with Wide Operating Range

Abstract This study investigates the interrelationship between shaft voltage (SV) and AC copper loss (ACCL) based on design variables that influence both characteristics. In previous works, issues with SV and ACCL have been reported in electric vehicle propulsion motors operating at high speeds. While methods to individually reduce these characteristics are well established, the correlation between them with respect to design variables has not yet been explored. To analyze this correlation, an analysis of the equations related to parasitic capacitances and ACCL is conducted to identify the key design variables affecting both SV and ACCL. These variables include the distance between the winding and the rotor, slot opening width, and winding width. Based on these design variables, a correlation analysis is conducted to confirm how these characteristics change simultaneously, and the results are verified through finite element analysis. Finally, an optimization process is implemented to minimize SV and ACCL while achieving the target average torque. The results are validated experimentally.

A Read-out Scheme of 1T-1D DRAM Design with Transistor Assisted Decoupled Sensing Amplifier in 7 nm Technology

ABSTRACT Dynamic random-access memory (DRAM) is one of the most widely used storage techniques. A conventional DRAM cell consists of one transistor and one capacitor. However, the standard read-out scheme has to be applied due to the relatively large bitline parasitic capacitance of the DRAM cells. Sensing amplifiers (SA) are used to detect and amplify minute voltage differentials in order to convert them into powerful and coherent logic signals. The proposed study uses improved peripheral designs to develop a DRAM based on a read-out strategy using a single transistor and one diode (1T1D). The improved transistor-aided decoupled SA (TADSA) based read-out scheme uses less energy than conventional designs. During the power gating phase of SA, an NMOS transistor reduces leakage by acting as a sleep transistor. The power consumption and read/write access time performance metrics are analysed in the simulation section for various CMOS technologies, supply voltages and NMOS gate lengths. The proposed design attains faster read (0.026 µs) and write access times (0.012 µs) and lower power dissipation (2.02 mW). Additionally, the effect of TADSA performance was evaluated in terms of power and delay by altering the decoupling of PMOS transistors’ width under different supply voltages.

Overrated energy storage performances of dielectrics seriously affected by fringing effect and parasitic capacitance

Dielectric capacitors are vital for modern power and electronic systems, and accurate assessment of their dielectric properties is paramount. However, in many prevailing reports, the fringing effect near electrodes and parasitic capacitance in the test circuit were often neglected, leading to overrated dielectric performances. Here, the serious impacts of the fringing effect and parasitic capacitance are investigated both experimentally and theoretically on different dielectrics including Al2O3, SrTiO3, etc. The deviations are more critical for the measurements of capacitors using asymmetric electrodes with different areas and for dielectrics with a lower dielectric constant, and differences tested in silicone oil and air environments should be noticed. A method to calibrate the parasitic capacitance of the test circuit is also raised for ensuring the accuracy of measured dielectric performances. Enlarging the electrode diameter and/or thinning the sample can reduce the above deviations, and thus a general standard of setting capacitor configurations is proposed for the measurement validity. Our study clearly demonstrates that it is necessary to mitigate the fringing effect and subtract the parasitic capacitance to solve the problem on overrated dielectric performances, which is very important for the development of the dielectric research in a healthy and orderly way.

The impact of parasitic capacitances on the accuracy of scale transformation of high-voltage dividers

Purpose. The aim of this work is the determination of the parasitic capacitance’s influence on the accuracy of scale transformation of high-voltage dividers. Analyzing the possibilities of reducing such influence is a pressing problem for high voltage measurement, especially at high frequency range of input voltage. Methodology. Mathematical modeling of the voltage divider equivalent circuit, considering parasitic capacitances and inductances has been performed in the QUCS circuit simulator software under sinusoidal alternating current conditions in the range from 100 Hz to 1 MHz. Using the FEMM software, the finite element method was used to simulate the density distribution of capacitive currents in the module with capacitance graded insulation of the high-voltage arm of the voltage divider. Results. The results of the calculations show that the percentage of parasitic capacitive currents decreases exponentially depending on the ratio of the outer radii of the shielding disks to the distance between them. However, even with the outer radii of the shielding disks of about 3 m, capacitive currents still make up about 1 % of the total current flowing in the measuring circuit of the voltage divider. Instead of increasing outer radii, it is proposed to use high-voltage capacitance graded insulation between the shielding disks. As a result, a stable error of large-scale voltage transformation was obtained when the values of parasitic capacitances change, and it is proposed to manufacture the high-voltage arm of the voltage divider from the same type of high-voltage modules. Originality. The results of modeling the dependence of the accuracy of the voltage divider scale transformation on the ratio of the structural elements geometric parameters of its high-voltage arm were obtained. The solution has been proposed that involves changing the design of the high-voltage arm of the voltage divider, which significantly reduces the dependence of its scale transformation error on significant changes in the parasitic capacitances of the structure components on grounded surfaces. Practical value. The results of mathematical modeling of the characteristics of the voltage divider high-voltage arm make it possible to design, for the purpose of serial production, the same type of high-voltage modules for assembling on-site broadband voltage dividers for any nominal voltage, which will have the possibility of integration into Smart Grid systems. References 23, tables 1, figures 8.

An Accurate, Universal, and Fast Time Domain Model for Different Types of Resonant Converters by Considering Parasitic Capacitors and Deadtime

An Accurate, Universal, and Fast Time Domain Model for Different Types of Resonant Converters by Considering Parasitic Capacitors and Deadtime

ITZO-Based Self-Aligned Top Gate Thin-Film Transistor with Minimum Parasitic Capacitance for Long-Retention 2T0C DRAM.

We developed a two-transistor, zero-capacitor (2T0C) gain-cell memory featuring a self-aligned top-gate-structured thin-film transistor (TFT) for the first time. The proposed indium tin zinc oxide (ITZO) channel-incorporated architecture was specifically engineered to minimize parasitic capacitance for achieving long-retention 2T0C memory operations. A typical 2T0C structure features five types of parasitic capacitances; however, the proposed SATG design effectively used an essential gate insulator capacitance (C OX) and reduced four nonessential capacitances (C WBL-WWL, C WWL-SN, C RWL-SN, and C RBL-SN) to virtually zero. The ITZO-based 2T0C gain-cell memory achieved a retention time >10,000 s owing to the extremely low off-current (2.33 × 10-18 A/μm), superior positive-bias stability (0.71 V), and high saturation mobility [17.52 cm2/(V s)] of the optimized TFT structure. Our proposed memory with long retention and high endurance is a promising solution for next-generation 3D-integrated stacked dynamic random-access memories and defines a new structural standard for future memory architectures.

Field-Programmable Gate Array-Based True Random Number Generator Using Capacitive Oscillators

In this paper, novel architecture of the true random number generator (TRNG) is presented. The proposed TRNG uses jitter in capacitive oscillators as a source of entropy. These capacitive oscillators exploit the input/output (I/O) buffers of a field-programmable gate array (FPGA) chip. A specific connection between these buffers allows cyclical charging and discharging of a parasitic capacitance associated with an external FPGA pin. If a few pins of an FPGA chip are not connected to any external components, they can be targeted to build the TRNG. The proposed TRNG requires only three external FPGA pins dedicated to capacitive oscillators, as well as 18 look-up tables (LUTs) and 20 flip-flops (FFs). Its throughput amounts to 11–13 Mbit/s. To pass all NIST SP800-22 statistical tests for a wide range of operating temperatures, the TRNG requires a post-processing circuit. The characteristic feature of the proposed TRNG is that it internally generates a signal indicating that a random bit was just produced. Therefore, no external clock signal is needed to sample the output.

A Study of Device Parameters Affecting the Current Error Rate in a Low-Temperature Polycrystalline Silicon Thin-Film Transistor Pixel Circuit for Active-Matrix Organic Light-Emitting Diode Display Applications

In active-matrix organic light-emitting diode (AMOLED) displays, conventional pixel circuits that compensate for the non-uniformity of the threshold voltage (VT) of low-temperature polycrystalline silicon thin-film transistors (TFTs) can hardly compensate for variations in other TFT parameters, such as carrier mobility (μ0), subthreshold swing (SS) and the various effects of parasitic capacitance. In recent high-resolution AMOLED displays, as the current required for OLED pixel driving decreases, the current error rate (CER) caused by the non-uniform TFT parameters increases. In this study, we analyzed the influence of each TFT parameter on the CER using SPICE simulation. Based on our analysis, the origin of the increased CER can be classified into two categories: the charging capability of driving TFT and the capacitive coupling effect of the switching TFT. The SS of the driving TFT and the parasitic capacitance of the switching TFT are major factors that affect the CER in terms of the charging capability and capacitive coupling effect, respectively. Our analysis results can be summarized as follows: The SS value of the driving TFT should be high, and its variation should be small to minimize the CER. The variation in the parasitic capacitance of the switching TFT possibly occurs due to long-term bias conditions, as well as process non-uniformity. Therefore, the stability of TFT should also be confirmed for the prevention of anomalous CER caused by long-term bias stress.

Analysis of trapping effects on DC and RF performance in double Π-gate Al0.3Ga0.7N/GaN MOSHEMTs

Abstract This study investigates trap analysis of the DC and RF performance of Al0.3Ga0.7N/GaN Metal-Oxide-Semiconductor high electron mobility transistor (MOSHEMT) with double π-gate technology. The motivation behind double π-gate technology is to evenly distribute the peak electric field and reduce hot electron generation. This gate design helps to lower hot-electron generation across various operating conditions while maintaining device performance, particularly in the lower millimeter-wave frequency range. High dielectric constant HfO2 is used as gate oxide, which helps to lower the gate leakage current. Near the conduction band (CB), the electron quasi-fermi level of 30 meV is achieved. The practical application of HfO2 in AlGaN/GaN HEMTs is limited by its high oxygen permeability, brittleness, and reactivity with moisture and CO2, which can cause mechanical stress and form hafnium carbonate, adversely affecting device performance. Future designs of the double-π gate structure could enhance electrostatic control, reduce short-channel effects, and improve high-frequency performance by scaling down gate dimensions and using high-k or novel dielectric materials. Additionally, optimization for mm-wave and THz applications would help to maintain electron mobility and minimize parasitic capacitance and resistance.

Design and Characterisation of an EIT Current Supply Module

Abstract Electrical Impedance Tomography is used to image the cross-sectional conductivity of an object. It is clinically used for high-frame-rate imaging of lung ventilation. Most current systems use very limited current injection wave-forms and patterns. We have developed a flexible system for researching alternatives. This paper covers our current supply module's design and characterisation. We tested the input filtering, Bandwidth, and parasitic capacitance. The imput fitering functioned similarly to the simulation of the design. However, the bandwich was limited to approximately 1 MHz instead of the desired 10 MHz due to excessive parasitic capacitance. We proposed points to redesign that should reduce the capacitance by a factor of 10 and correspondingly increase dandwidth tenfold to 10 MHz.

ЛОГАРИФМІЧНІ АНАЛОГО-ЦИФРОВІ ПЕРЕТВОРЮВАЧІ. ОГЛЯД

In this work, a review of logarithmic analog-to-digital converters (LADCs) was carried out and an analysis of their properties in the dynamic range of input signals of 80 dB was carried out. It is shown that the highest metrological characteristics are obtained by LADCs on switched capacitors (CC) using high-quality analog switches from Maxima and Analog Devices companies, in which parasitic interelectrode capacitances do not exceed 1 pF. LADC of different classes were considered. Serial LADCs on CC have the lowest speed, they are performed with redistribution or accumulation of charge (RC or AC) in capacitor cells, in which switching is carried out with analog switches; in such LADCs, the conversion error can be reduced to 0.25% (taking into account the quantization error of 0.1%) with a conversion time of no more than 20 ms. The same speed has LADC with pulse feedback, the conversion error of which is almost completely determined by the value of the quantization error for values ​​of the last 0.1% and more. Interpolation LADCs make it possible to reduce the conversion error below 0.1% with a conversion time of the order of hundreds of microseconds. Medium-speed LADCs with a conversion time of 100 μs or less include subband, recurrent, and bit-by-bit, which achieve a conversion error of 0.005%, 0.0015%, and 0.0015%, respectively. High-speed LADCs are parallel, their conversion error does not exceed 0.4% with a conversion time of less than 10 ns. Key words: logarithmic ADCs, construction, characteristics, parameters

ЛОГАРИФМІЧНІ АНАЛОГО-ЦИФРОВІ ПЕРЕТВОРЮВАЧІ. ОГЛЯД

In this work, a review of logarithmic analog-to-digital converters (LADCs) was carried out and an analysis of their properties in the dynamic range of input signals of 80 dB was carried out. It is shown that the highest metrological characteristics are obtained by LADCs on switched capacitors (CC) using high-quality analog switches from Maxima and Analog Devices companies, in which parasitic interelectrode capacitances do not exceed 1 pF. LADC of different classes were considered. Serial LADCs on CC have the lowest speed, they are performed with redistribution or accumulation of charge (RC or AC) in capacitor cells, in which switching is carried out with analog switches; in such LADCs, the conversion error can be reduced to 0.25% (taking into account the quantization error of 0.1%) with a conversion time of no more than 20 ms. The same speed has LADC with pulse feedback, the conversion error of which is almost completely determined by the value of the quantization error for values ​​of the last 0.1% and more. Interpolation LADCs make it possible to reduce the conversion error below 0.1% with a conversion time of the order of hundreds of microseconds. Medium-speed LADCs with a conversion time of 100 μs or less include subband, recurrent, and bit-by-bit, which achieve a conversion error of 0.005%, 0.0015%, and 0.0015%, respectively. High-speed LADCs are parallel, their conversion error does not exceed 0.4% with a conversion time of less than 10 ns. Key words: logarithmic ADCs, construction, characteristics, parameters

High‐Q LNA With a VCO for Small Calibration Frequency Errors

ABSTRACTA high‐quality (Q) low‐noise amplifier (LNA) combined with a voltage‐controlled oscillator (VCO) is presented for small frequency errors in self‐calibration. The proposed new double capacitive‐cross‐coupled structure controls negative impedance and thus, changes the working mode between the LNA and VCO with a small variation of parasitic capacitance, which results in a small calibration frequency error. High‐Q and low‐noise performances were theoretically analyzed and confirmed by simulation and measurement. The measured LNA operated from 2.2 to 2.44 GHz with a Q‐factor of 34 while the frequency offset was less than 0.9%. A power gain of 27 dB, noise figure of 2.1 dB, and input third‐order intercept point (IIP3) of −17 dBm were obtained while the power dissipations of the LNA and VCO modes were 10.2 and 4.7 mW from a 1.5‐V supply, respectively.

A Simple Characterization Method for Parasitic Capacitance Extraction of SiC Power MOSFETs Integrated Half-Bridge Configuration

A Simple Characterization Method for Parasitic Capacitance Extraction of SiC Power MOSFETs Integrated Half-Bridge Configuration

Effect of differently shaped spiral inductors on micro power integrated circuit

Abstract This paper investigates the impact of parasitic effects on the performance of on-chip planar spiral inductors for DC-DC converter applications, focusing on three geometries: square, hexagonal, and octagonal. Detailed electromagnetic simulations in MATLAB are employed to analyze the frequency-dependent behavior of key parasitic components, including ohmic resistance (Rs), substrate resistance (Rsub), oxide capacitance (Cox), and substrate capacitance (Csub) across a frequency range of 1 GHz to 10 GHz. The study reveals that the octagonal spiral inductor outperforms the others, demonstrating a 29% reduction in ohmic resistance at 1.5 GHz compared to the square geometry and achieving the highest substrate resistance, which helps reduce current leakage. Additionally, the octagonal inductor exhibits the lowest parasitic capacitance and a high-quality factor, peaking at 30 at 4.2 GHz. These results underscore the significant impact of inductor geometry on minimizing energy dissipation and electromagnetic interference, positioning the octagonal spiral inductor as a compelling choice for enhancing efficiency and miniaturization in DCDC converter designs.

A 43.5dB Gain Unipolar a-IGZO TFT Amplifier with Parallel Bootstrap Capacitor for Bio-signals Sensing Applications.

In this paper, a high gain amplifier with phase compensation loop is presented. A structure of parallel gate cross-coupled transistors to both ends of differential pair drain and source is designed to improves the load impedance, which obtains sufficient gain and further reduces power consumption. A novel capacitor bootstrap load circuit is proposed. The capacitor bootstrap topology is constructed by the drain source resistance of the transistor working in the cut-off region, where the gate source parasitic capacitor of the transistor is in parallel with the bootstrap capacitor rather than the existing series structure, thereby only a small bootstrap capacitor is required. By avoiding the use of large capacitors, chip area can be effectively reduced without compromising performance such as gain and bandwidth. The amplifier is fabricated using 10-μm n-type a-IGZO TFT technology. Measurement results show that the proposed amplifier achieves a voltage gain of 43.5dB and a common mode rejection ratio of 61.2dB while maintaining low power consumption. The amplifier also exhibits a -3dB bandwidth covering 0.4~2.1KHz, encompassing major bioelectric frequency bands. A real-time ECG signal was successfully captured using the fabricated TFT amplifier and gel electrodes. It has great potential in flexible sensing and acquisition applications such as electro cardiogram (ECG), electro encephalogram (EEG), pulse detection, and other wearable applications.

Accurate Evaluation of Commutations of 650 V GaN Power Switches Assisted by Electromagnetic Simulations in a 7 kW Dual Active Bridge Converter for Automotive Battery Charging Applications

The exploitation of high-voltage GaN power switches enables the development of power converters with superior characteristics with respect to components developed with heritage silicon-based technologies. One of the key advantages of GaN switches is their very fast commutation capability due to reduced parasitic capacitance and inductance with respect to silicon devices. The capability of an accurate evaluation of the switch commutations in the design phase is of crucial importance to maximize performance and avoid reliability or electromagnetic compatibility issues in the final converter. In this paper, an accurate evaluation of high-voltage GaN HEMT commutations is performed, exploiting detailed non-linear dynamic models of transistors and electromagnetic simulations of a PCB. A deep insight into the commutation waveforms in the intrinsic device (i.e., conductive drain current and intrinsic node voltages) is proposed to evaluate and explain the mechanisms of almost lossless turn-off and turn-on commutations in a 7 kW DAB converter. The influence on the performance of the PCB parasitics and the driver characteristics are accurately reproduced by simulations, suggesting important guidelines for the optimal design of power converters fully exploiting GaN HEMT’s potential. This detailed simulation/analysis approach for transistor commutation is typically adopted in Radio Frequency amplifier design but also becomes very valuable in power converter design when the very fast commutations of a GaN HEMT at a high switching frequency cannot be fully described and taken under control with conventional approaches used in power electronics design. The simulation results are confirmed by experimental data.

Reducing Avalanche Build-Up Time by Integrating a Single-Photon Avalanche Diode with a BiCMOS Gating Circuit.

It is shown that the integration of a single-photon avalanche diode (SPAD) together with a BiCMOS gating circuit on one chip reduces the parasitic capacitance a lot and therefore reduces the avalanche build-up time. The capacitance of two bondpads, which are necessary for the connection of an SPAD chip and a gating chip, are eliminated by the integration. The gating voltage transients of the SPAD are measured using an integrated mini-pad and a picoprobe. Furthermore, the gating voltage transients of a CMOS gating circuit and of the BiCMOS gating circuit are compared for the same integrated SPAD. The extension of the 0.35 μm CMOS process by an NPN transistor process module enabled the BiCMOS gating circuit. The avalanche build-up time of the SPAD is reduced to 1.6 ns due to the integration compared to about 3 ns for a wire-bonded off-chip SPAD using the same n+ and p-well as well as the same 0.35 μm technology.

A small area-occupation three-stage OTA with transistor resistance and parasitic capacitance Q-factor modulation for miniaturized communication systems

A small area-occupation, three-stage operational transconductance amplifier (OTA) is proposed for miniaturized communication systems. Our work presents a novel RC impedance attenuation solution composed of transistor resistance and parasitic capacitance mainly modulating the Q-factor (TRPCQM) of complex poles and precisely handles the first zero and the second pole to enlarge unity-gain frequency (UGF). By employing source-drain transconductance equivalent resistance and inexpensive parasitic capacitance in our RC impedance attenuation block, the complex poles can be regulated meanwhile decreasing chip area occupation. Under a supply voltage of 1.2V, the proposed design is validated using a standard 0.18 μm CMOS process, occupying an ultra-small area of 0.00276 mm2. When driving an ultra-large load of over 20 nF, the design achieves a DC gain exceeding 110 dB and a unity-gain frequency (UGF) of more than 2.1 MHz, with a power consumption of only 10.46 μW.

Interpretation of Impedance Spectra for Neural Stimulation Devices in Vitro

The interpretation of the physical properties of any given electrode device requires precise models for analyzing the impedance spectroscopy data and assessment of the data consistency with the Kramers-Kronig relations. In 1992, Shannon [1] studied the influence of charge reactions and charge density on macro electrodes and proposed safe levels of electrical stimulation for macro electrodes employed in brain stimulation. However, the current density performance of neural stimulation devices is dependent on the electrode size. By considering the contributions of both charging and faradaic current densities on the impedance spectroscopy data for microelectrode and ultra-microelectrode devices, we aim to develop accurate models and provide reliable data interpretation for the physical properties of neural stimulation devices.We conducted electrochemical impedance spectroscopy (EIS) measurement for our 32-channel ultramicroelectrode device with site diameters ranging from 5 microns to 10 microns. The experiment was performed with the Gamry Reference 600+ Potentiostat, at open circuit conditions. The three-electrode-cell configuration consists of the working electrode, an Ag/AgCl reference, and a Platinum mesh counter electrode, immersed in phosphate-buffered saline. Impedance measurements were collected at an applied AC voltage of 25 mV rms with a frequency sweep from 10 kHz to 0.2 Hz at 10 points per decade.The limits of the EIS measurements were assessed by plotting the accuracy contour plot for the Gamry Reference 600+ Potentiostat and the Reference 600+ Potentiostat connected to the 32-channel ultramicroelectrode device by a junction box. Methods for assessing potentiostat limits followed Gamry's recommendations, including open and shorted lead EIS measurements [2]. The accuracy of impedance measurement for the ultramicroelectrode device was evaluated using loops and terminal features on the device that enabled closed-circuit and open-circuit measurements, respectively.The EIS data for the smaller electrodes (with diameters of 10 microns and 5 microns) were influenced by the capacitance of the cables; whereas, the larger/reference electrode (with an area of 4004 square microns) was unaffected by cable capacitance but was affected by ohmic impedance. The impedance spectra of the ultramicroelectrode device were regressed with a measurement model program [3] to compute the stochastic error structure and obtain parameters for accurate interpretation of the electrodes’ properties. Most of the data was consistent with the Kramers-Kronig relations.The circuit element for the parasitic capacitance was added to the process model to fit the data points affected by the cable capacitance at high frequency. At open circuit, the model accounted for the constant element behavior of the electrode, and mass-transfer influenced by oxygen-reduction reactions. The capacitance of the electrodes was estimated by the application of Brug’s formula to the fitting parameters obtained from the process model analysis and the measurement model regression results. The capacitance calculated with the measurement model was consistent with the values of the parasitic capacitance obtained from the process model regression analysis.