Photodiode Capacitance Research Articles

Photodiode Peripheral Utilization Effect on CMOS APS Pixel Performance

A photodiode (PD)-type CMOS active pixel sensor (APS) pixel is comprised of a reverse-biased p-n-junction diode (PD) for photon conversion and charge storage, and a number of MOS transistors. Junction capacitance of the PD has two major components; bottom plate (area) and side wall (periphery). Both play important roles in the electro-optical performance of PD-APS pixels. This paper reports PD peripheral junction utilization effects on the pixel's electro-optical performance, full-well capacity and spectral response for an 18times 18 mum CMOS PD-APS pixel were improved by opening multiple circular holes in the PD diffusion layer. A prototype CMOS APS imager was designed, fabricated, and tested in 0.5-mum, 5 V, 2P3M CMOS process, containing a 424 times 424 pixel array with smaller sub-arrays for multiple pixel designs. Four test pixels with 7, 11, 14, and 17 circular, 1.6-mum-diameter holes were placed on one pixel array, with one control pixel for reference. Pixel characteristics, dark current, PD capacitance, quantum efficiency, sensitivity, and pixel full-well capacity were measured. It was found that increased PD junction peripheral would potentially help to improve total capacitance of the PD, with the expense of higher dark current. We also found that increased PD peripheral capacitance improves spectral response up to 12% of the PD-APS pixel, especially at short wavelengths.

Measurement and comparison of silicon p-i-n-photodiodes with ac impedance at different voltages

The dark alternating current (ac) parameters of commercially available silicon p-i-n-photodiodes are measured and compared at room temperature both in forward and reverse bias using the impedance spectroscopy technique. The ac behavior of the photodiodes is found to be almost the same. For bias voltages in the range from −0.8 to 0.0 V, the typical photodiode behaves like a pure capacitor. For higher voltages (V >-0.2 V) the impedance spectra are nearly semicircular and typically distorted on the high frequency side. At 0.2 V the distortion apparently arises from one of the two interfaces. However, at high bias voltages the nature of the distortion is attributed to the variation of photodiode capacitance and resistance with measurement frequency.

Optical Receiver With Widely Tunable Sensitivity in BiCMOS Technology

A monolithically integrated optical receiver with voltage-controlled sensitivity in 0.6-m BiCMOS technology is presented. The transimpedance variations are achieved by varying the control voltage of the voltage-controlled resistor changing its equivalent resistance. The optical receiver design is based on a P-intrinsic-N photodiode and on a mixed current-mode and voltage-mode approach, by using a current conveyor and a voltage amplifier. Thanks to the current-mode signal processing, the bandwidth of the optical receiver is independent of the photodiode capacitance. A linearity error smaller than 2.92%, a sensitivity dynamic range of 83.2 (38.4 dB), an offset voltage smaller than 0.56 mV, a power consumption less than 4.7 mW, and a bandwidth up to 205.5 MHz are achieved.

A Dynamic Optically Reconfigurable Gate Array—Perfect Emulation

This paper presents a perfect dynamic optically reconfigurable gate array (DORGA) architecture emulation using a holographic memory and a conventional ORGA-VLSI. In ORGAs, although a large virtual gate count can be realized by exploiting the large-capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, a DORGA architecture has been proposed in order to increase the gate density. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, demonstration of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. Therefore, in this study, the DORGA architecture was perfectly emulated, and the performance, particularly the reconfiguration context retention time, was measured experimentally. The advantages of this architecture are discussed in relation to the results.

イメージセンシング技術とその応用 負帰還イメージセンサを用いたフレーム内動き方向検出処理

We investigated a negative feedback method for adding functionality to a CMOS image sensor. Our sensor effectively uses the method to set any intermediate voltage into a photodiode capacitance while a pixel circuit is in motion. The negative feedback reset functions as a noise cancellation technique and can obtain intermediate image data during charge accumulation. Using the above features, we achieved duplicated interlaced processing and were able to output frame-difference images without frame buffers. The experimental results obtained with a chip fabricated using a 0.25-μm CMOS process demonstrate that intra-frame motion detection is an effective application of negative feedback resetting.

Silicon photodiode with a grid p-n junction

Silicon photodiodes with a grid-structured p-region were studied. Analytical expressions for the capacitance of such photodiodes were derived. The influence of the cell sizes and diffusion length of minority carriers on the sensitivity of the silicon grid photodiode was analyzed in a spectral range of 0.6–1.0 μm. The experimental characteristics of photodiodes with a grid p-n junction with cell sizes of 50 and 110 μm are given. The factors controlling the spectral-characteristic features of these photodiodes are discussed.

A Wide-Dynamic-Range Compression Image Sensor With Negative-Feedback Resetting

A CMOS image sensor capable of wide-dynamic-range compression is proposed. This sensor has two main features. It uses a negative-feedback technique to set any intermediate voltage into photodiode (PD) capacitance in the pixel circuit. It also uses a quasi-holding function by resetting the pixel-output voltage into PD capacitance. Dynamic range compression is achieved by individually selecting pixels and by setting an intermediate voltage or performing quasi-holding with respect to each pixel. Output data has a polygon-like form corresponding to a change from high sensitivity to low sensitivity as optical intensity becomes stronger. Experimental results obtained with a chip fabricated using a 0.25-mum CMOS process demonstrate dynamic range compression

Broad-Band Design Techniques for Transimpedance Amplifiers

In this paper, a novel bandwidth enhancement technique based on the combination of capacitive degeneration, broad-band matching network, and the regulated cascode (RGC) input stage is proposed and analyzed, which turns the transimpedance amplifier (TIA) design into a fifth-order low-pass filter with Butterworth response. This broad-band design methodology for TIAs is presented with an example implemented in CHRT 0.18-mum 1.8-V RF CMOS technology. Measurement data shows a -3-dB bandwidth of about 8 GHz with 0.25-pF photodiode capacitance. Comparing with the core RGC TIA without capacitive degeneration and broad-band matching network, this design achieves an overall bandwidth enhancement ratio of 3.6 with very small gain ripple. The transimpedance gain is 53 dBOmega with a group delay of 80plusmn20 ps. The chip consumes only 13.5-mW dc power and the measured average input-referred noise current spectral density is 18 pA/radicHz up to 10 GHz

Measurement and comparison of complex impedance of silicon p-i-n photodiodes at different temperatures

The dark alternating current (ac) parameters of BPW34 and BPW41 (Vishay-Telefunken) silicon p-i-n photodiodes are measured and compared at different temperatures using the impedance spectroscopy technique. The impedance plots are nearly semicircular and typically distorted on the high frequency side. For BPW41, the distortion apparently arises from one of the two interfaces as expected for a typical p-i-n device. However, for BPW34, the presence of the distortion is attributed to the variation of photodiode capacitance and resistance with measurement frequency.

Low-Power BiCMOS Optical Receiver With Voltage-Controlled Transimpedance

An optical receiver with voltage-controlled transimpedance using a current conveyor and a voltage amplifier monolithically integrated with a PIN photodiode in 0.6 mum BiCMOS technology is presented. The transimpedance is directly proportional to a voltage-controlled resistance, and can be continuously varied by changing its control voltage. Thanks to the mixed current-mode and voltage-mode signal processing, the bandwidth of the optical receiver is virtually independent of the photodiode capacitance. A linearity error smaller than 3.1%, a sensitivity dynamic range of 78.8 (37.9 dB) with the largest sensitivity of S = 890 mV/muW at 660 nm, an offset voltage smaller than 0.53 mV, a largest maximum power consumption of only 3.2 mW, a small-signal frequency bandwidth up to 189 MHz, a large-signal rise time/fall time down to 3.7 ns/3.3 ns, and an output noise level down to -77.8 dBm (for a frequency of 50 MHz and a resolution bandwidth of 30 kHz) are achieved.

CMOS Image Sensor Using Negative-Feedback Resetting to Obtain Variably Smoothed Images

We designed a CMOS image sensor capable of capturing variably smoothed images. This sensor uses a negative-feedback technique to set photodiode (PD) capacitance in the pixel circuit to any intermediate voltage during charge accumulation and it provides a neighboring-pixel operation by using their average value when resetting the PD capacitance. Smoothing-filter coefficients are changed by adjusting timing of the pixel-readout and neighboring-pixels operations. The performance of the proposed sensor was evaluated by SPICE simulation and numerical analysis.

6 GHz transimpedance amplifier for optical sensing system in low-cost 0.35 µm CMOS

A high-speed transimpedance amplifier (TIA) has been designed and implemented in a low cost 0.35 µm CMOS technology. Combining the techniques of regulated cascode input stage, current shunt feedback and inductive-series peaking, the TIA achieves a transimpedance gain of 51 dBΩ and 3 dB bandwidth of 6 GHz, in the presence of a photodiode capacitance of 0.6 pF. This is believed to be the fastest TIA ever reported in 0.35 µm CMOS technology.

220-MHz monolithically integrated optical sensor with large-area integrated PIN photodiode

We propose a PIN photodiode integrated in a BiCMOS process which combines a quantum efficiency of nearly 100% for red light, fast response times, and a low junction capacitance. Bandwidths of 720 MHz at 660 nm and 683 MHz at 850 nm are achieved for this PIN photodiode. It allows the design of fast optoelectronic integrated circuits for many advanced applications in optical sensing, optical storage systems, and optical data transmission for optical wavelengths ranging at least from 660 to 850 nm. Because of the low photodiode capacitance of 0.01 fF//spl mu/m/sup 2/, it is possible to achieve high bandwidths, even with large photodetector areas. The proposed optical receiver employing a PIN photodiode with a diameter of 500 /spl mu/m and a capacitance of only 2.2 pF attains a -3-dB bandwidth of 220 MHz, which corresponds to a maximum nonreturn-to-zero data rate of 300 Mbit/s.

Highly linear BiCMOS optical receiver with voltage-controlled sensitivity

An optical receiver with voltage-controlled resistor based variable sensitivity in 0.6 µm BiCMOS technology is presented. The bandwidth is independent of the photodiode capacitance. A linearity error smaller than 2.86%, a sensitivity dynamic range of 56 (35 dB), an offset voltage smaller than 0.51 mV, a bandwidth up to 204 MHz, and a power consumption less than 5.7 mW are achieved.

A New Differential CMOS Current-Mode Preamplifier for GBps Data Communications

This paper presents a new low-voltage fully differential CMOS current-mode preamplifier for GBps data communications. The number of transistors between the power and ground rails is only two so that the minimum supply voltage is one threshold voltage plus one pinch-off voltage. The preamplifier is a balanced two-stage configuration such that the effect of bias-dependent mismatches is minimized. A new inductive series-peaking technique is introduced to increase the bandwidth by utilizing the resonance characteristics of LC networks. In addition, a new negative differential current feedback technique is proposed to boost the bandwidth and to reduce the value of peaking inductors. The preamplifier has been implemented in TSMC 0.18 ?m, 1.8 V, 6-metal mixed-mode CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. For an optical front-end with a 0.3 pF photodiode capacitance, simulation results demonstrate that the preamplifier has bandwidth of 3.5 GHz and provides a transimpedance gain of 66 dB?. The total chip area is approximately 1 mm2 and the DC power consumption is about 85 mW.

A CMOS infrared wireless optical receiver front-end with a variable-gain fully-differential transimpedance amplifier

A CMOS infrared wireless optical receiver front-end is presented. A stable variable-gain fully-differential transimpedance feedback amplifier is designed employing a current-mode amplifier as the feedforward gain element. More than a triple variation of the transimpedance gain, from 0.3 k/spl Omega/ to 1 k/spl Omega/, the variable-gain transimpedance amplifier achieves desirable gain-bandwidth independence. For an infrared wireless optical receiver front-end employing the transimpedance amplifier, the optical preamplifier achieves a transimpedance gain of 66 dB/spl Omega/ and a bandwidth of 114 MHz with a 5 pF photodiode capacitance, and a power consumption of 17.4 mW.

Design of high-performance photodiode receivers for optical tomography

The design of instrumentation hardware for tomographic systems must take careful account of measurement noise. This is especially true in near-infrared absorption tomography, where the signal of interest is typically only a few percent of the total signal at the detector, and the available optical power may have to be shared among many measurement channels. In this paper, the monitoring of photodiodes in near-IR absorption tomography is examined in detail, but much of the material is applicable at wavelengths ranging from the UV to beyond 2.5 /spl mu/m. The authors' application involves the frequency region 50 kHz to 2 MHz, which lies above that utilized in the majority of radiometric sensing systems, yet substantially below telecoms bit rates. The problem is further distinguished by the use of phase-sensitive detection schemes, which make local noise density more relevant than wideband noise performance and relax the requirement for dc precision. Alternative transimpedance circuit configurations, including both single-ended and differential topologies, are analyzed with a view to optimization of the signal-to-noise ratio. Typical values of photodiode capacitance and shunt resistance are shown to result in significant noise gain, greatly increasing the importance of amplifier voltage noise relative to other intrinsic noise sources. It is shown that for applications of this type, viable alternatives to the traditionally dominant FET amplifier do exist. The relative susceptibility to coupled interference is also considered. The results of practical tests, involving class-leading operational amplifiers, are presented to support the analyses. These results also underline the need for careful circuit layout and shielding if the capabilities of these devices are to be fully exploited.

20 mW 1.25 Gbit/s CMOS transimpedance amplifier with 30 dB dynamic range

A 1.25 Gbit/s transimpedance amplifier using a novel photodiode capacitance cancellation technique has been demonstrated in 0.35 µm CMOS technology. The transimpedance amplifier achieved a transimpedance gain of 17.1 kΩ as well as a wide dynamic range from +1 to −29 dBm while consuming only 20 mW from a 3 V supply.

Bandwidth enhancement for transimpedance amplifiers

A technique for bandwidth enhancement of a given amplifier is presented. Adding several interstage passive matching networks enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using well-known low-pass filter component values, is introduced. To demonstrate the feasibility of the method, a CMOS transimpedance amplifier (TIA) is implemented in a 0.18-/spl mu/m BiCMOS technology. It achieves 3 dB bandwidth of 9.2 GHz in the presence of a 0.5-pF photodiode capacitance. This corresponds to a bandwidth enhancement ratio of 2.4 over the amplifier without the additional passive networks. The transresistance gain is 54 dB/spl Omega/, while drawing 55 mA from a 2.5-V supply. The input sensitivity of the TIA is -18 dBm for a bit error rate of 10/sup -12/.

1-Gb/s 80-dB/spl Omega/ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects

A 1-Gb/s differential transimpedance amplifier (TIA) is realized in a 0.25-/spl mu/m standard CMOS technology, incorporating the regulated cascode input configuration. The TIA chip is then integrated with a p-i-n photodiode on an oxidized phosphorous-silicon (OPS) substrate by employing the multichip-on-oxide (MCO) technology. The MCO TIA demonstrates 80-dB/spl Omega/ transimpedance gain, 670-MHz bandwidth for 1-pF photodiode capacitance, 0.54-/spl mu/A average input noise current, -17-dBm sensitivity for 10/sup -12/ bit-error rate (BER), and 27-mW power dissipation from a single 2.5-V supply. It also shows negligible switching noise effect from an embedded VCO on the OPS substrate. Furthermore, a four-channel MCO TIA array is implemented for optical interconnects, resulting in less than -40-dB crosstalk between adjacent channels.