Capacitance Of MOSFET Research Articles

Modeling the Influence of Thermal Phenomena in Inductors and Capacitors on the Characteristics of the SEPIC Converter

The paper presents the results of measurements and calculations of the SEPIC converter characteristics, taking into account thermal phenomena in semiconductor devices and passive elements. Compact electrothermal models of the MOSFET transistor, diode, capacitor, and inductor are proposed. Parasitic phenomena are also included in these models. The form of the developed models and the method of determining the values of their parameters are presented. The correctness of the formulated models was verified experimentally. Calculations and measurements of the characteristics of SEPIC converters containing inductors with ferromagnetic cores made of different materials were carried out. The obtained results of the investigations are discussed, and the range of applicability of the formulated models is described. It was shown that, at the considered operating conditions at an ambient temperature equal to 22 °C, the temperature of capacitors can exceed 40 °C, whereas the temperatures of inductors can even reach 50 °C.

Modeling of inversion layer capacitance of III-V double gate MOSFETs using a neural network-based regression technique

Modeling of inversion layer capacitance of III-V double gate MOSFETs using a neural network-based regression technique

Confluence of Integrated Magnetics and TCM for a ZVS Based Higher Order Differential-Mode Rectifier

Two driving performance metrics in modern power-electronic systems are power density and efficiency: usually, improvement in one result in sacrificing the other. In this paper, triangular conduction mode (TCM) is used alongside integrated magnetics to achieve both performance metrics simultaneously. TCM is implemented by extending the switch current high enough to reverse direction and provide enough energy at the onset of the deadtime to discharge the parasitic capacitance of the SiC MOSFET. The elevated current ripple is alleviated by distributing the rectifier low-frequency current among parallel interleaved sub-modules. Taking advantage of the symmetrical topology of the differential mode Ćuk rectifier (DMCR), an integrated interleaved magnetic (IIM) structure is proposed to house all the inductors in a module. In doing so flux cancellation technique is used between the Ac-and Dc-side inductors to reduce the losses and size while using a custom core structure to control the flux coupling between the interleaved windings. A step by step design algorithm is presented to manage the different types of coupling within IIM. Challenges in design, fabrication, and testing of the system are analyzed and appropriate solutions are presented in each section. The solutions are supported by mathematical analysis to optimize the power stage design and validated by circuit as well as finite element simulations. An experimental setup is assembled to test this concept and multiple time-domain and parametric results are presented for proof of the concept in rectifier mode and single module mode.

Research on the Voltage Spike Suppression Strategy for Three-Phase High Frequency Link Matrix-Type Inverter

The problem of high-voltage spikes on the secondary side of a high-frequency transformer (HFT) in the commutation process of a three-phase high-frequency link matrix-type inverter (HFLMI) is studied. Considering the parasitic capacitance of MOSFETs, the mechanism of voltage spikes during HFLMI commutation is revealed. According to the characteristics of the topology, the later stage matrix converter (MC) is decoupled into two groups of conventional three-phase voltage type inverters by the de-re-coupling idea, and the space vector pulsewidth modulation (SVPWM) is carried out, respectively. The zero vector is inserted between two nonzero voltage vectors to accomplish smooth commutation for addressing the problem of voltage overshoot on the secondary side of HFT due to the switching of HFT leakage inductance and filter inductance to the same path. Due to the existence of parasitic capacitance, the voltage spikes caused by its resonance with the system’s stray inductance cannot be solved by optimizing modulation strategies. In order to further suppress voltage spikes, a flyback clamp circuit is proposed to absorb the leakage inductance energy. Ultimately, a prototype with a rated power of 200 W is developed for experimental verification. The results show that the peak efficiency of three-phase HFLMI with the flyback clamp circuit is 92.6% in the full power range, the voltage spikes on the secondary side of HFT are clamped to about 1.2 times the rated voltage, and all switches realize soft-switching.

Miller Capacitance Cancellation to Improve SiC MOSFET's Performance in a Phase-Leg Configuration

The drain to gate capacitance (Miller capacitance) of SiC MOSFETs leads to the Miller effect during switching transients. The Miller capacitance in a phase-leg configuration causes the crosstalk, the interaction between the two complementary switches, and the Miller plateau during the switching transient. The Miller effect reduces the switching speed, reduces reliability, and increases electromagnetic interference. In this article, by injecting a mirror cancellation current, the effects of Miller capacitance are canceled. The proposed technique includes a two-stage sensing and injection network to compensate for the nonlinearity of the Miller capacitance. The proposed technique can suppress both positive and negative gate voltage spikes induced by the crosstalk and reduce the switching power loss with the increased switching speed. Because no external control signals are required in the proposed technique, it can work with almost all commercial gate drivers. The detailed design for this proposed technique is presented in this article. The proposed technique was validated with both simulations and experiments.

Electrothermal Analysis of the Charge–Discharge Related Energy Loss of the Output Capacitance in OFF-State Superjunction MOSFETs

The charge-discharge-related loss of the output capacitance ( C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</sub> ) in OFF-state Superjunction (SJ) MOSFETs, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DISS</sub> , is a new source of energy loss limiting the frequency of soft-switched SJ MOSFETs. This article studies the electrothermal effect in C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</sub> during the charging and discharging processes with the help of numerical electrothermal simulations. The results show that energy is lost during both charging and discharging processes, mainly contributed by Joule heat that is caused by the movement of carriers in lightly doped drift regions. The fluctuant doping profile in a SJ MOSFET constructed with the multi-implant multi-epitaxy technology compresses the width of the path of charging and discharging currents at concentration valleys and causes high-current density. Then, its <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DISS</sub> is larger than that of the SJ MOSFET constructed with the trench-filling epitaxial growth technology. For an advanced device with a smaller cell-pitch, the width of the current path becomes narrower. Then, the current density decreases, and so does its <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DISS</sub> .

Accuracy of Three Interterminal Capacitance Models for SiC Power MOSFETs Under Fast Switching

This article presents a comprehensive analysis of nonlinear voltage-dependent capacitances of vertical silicon carbide power MOSFETs with lateral channel, focusing specifically on fast switching transients. The capacitance-voltage (C-V) device characteristics, (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> , C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> , C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> ), being dependent on both V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> , are extracted by means of two-dimensional technology computer aided design simulations for a commercially available device in both off- and on-state modes. Different compact models for the power MOSFET are investigated, each employing a three interterminal capacitance model as typically used in power electronics. The performed analysis provides a detailed explanation for the importance of taking into account the dependence of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> , C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> , and C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> on both of the voltages V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> . This is especially important for fast switching transients (in the range of 10 ns) in order to accurately predict switching losses, driver losses, current, and voltage slopes, as well as current and voltage delays. As direct measurements for C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> , C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> , and C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> in dependence of both V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> are highly demanding, the results presented in this article increase the understanding of both the underlying effects as well as of the tradeoffs between accuracy and computational complexity made by simplifying device models. In turn, this information is highly beneficial for enabling accurate and computationally efficient automated design procedures for power electronics.

Investigation on Ultralow Turn-off Losses Phenomenon for SiC MOSFETs With Improved Switching Model

Traditional SiC MOSFET switching models cannot predict the turn-off losses precisely in the condition of small driver resistance and small load current, because they have not considered a special case in which the SiC MOSFET closes its channel before the SiC diode turns into the freewheeling-state during turn-off transient. To solve this problem, this article presents an improved SiC MOSFET turn-off model that considers the special case. The parasitic elements of circuit and the nonlinear characteristics of SiC MOSFET are also included in the proposed model to improve its accuracy. Experimental results show that the improved model can predict the turn-off transient of SiC MOSFET precisely. Moreover, the investigation of turn-off behavior shows that SiC MOSFET can achieve ultralow turn-off loss in the special case, because the channel current of SiC MOSFET can fall to 0 before the drain-source voltage rises to a high value. Driver resistance and load current are the decisive factors of achieving the special case, and this article gives the criterion of them. Besides, further studies show that lower common-source inductance, larger drain-source capacitance of MOSFET, and larger capacitance of diode can help to achieve ultralow turn-off loss. Experiments are carried out and the experimental results verify the analysis results.

Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers

This article presents a novel implementation scheme of the essential circuit blocks for high-performance, full-precision Booth multipliers leveraging a hybrid logic style. By exploiting the behavior of parasitic capacitance of MOSFETs, a carefully engineered design style is employed to reduce dynamic power dissipation while improving the glitch immunity of the circuit blocks. The circuit-level techniques along with the proposed signal-flow optimization scheme prevent the generation and propagation of spurious activities in both partial-product and adder-tree stages. Two full-precision Booth multipliers built from proposed strategies were compared to the state-of-the-art versions known from literature by means of extensive post-layout simulations in 65-nm CMOS technology. The proposed versions on average demonstrated up to 10% and 30% power savings in general.

Modeling of Surface Potential and Fringe Capacitance of Selective Buried Oxide Junctionless Transistor

The Selective Buried Oxide-Charge Plasma based Junctionless Transistor (SELBOX-CPJLT) is a new upcoming device used mainly for reducing self-heating effects and second order effects. In this paper, 2D mathematical modeling of Surface Potential for SELBOX-CPJLT using Poisson’s equation has been proposed. We have modelled the fringe capacitance for SELBOX-CPJLT with the help of conformal mapping. SELBOX structure is a novel idea to counter the self-heating effect which is present in the SOI technologies. Implementation of the charge plasma on SELBOX based JLT MOSFETs is called as SELBOX-CPJLT. The electrostatic performance and the lattice temperature of SELBOX-CPJLT is also compared with the SELBOX-JLT in this paper. The simulation results show that the SELBOX-CPJLT device has low Drain Induce Barrier Lowering (DIBL) effect, Subthreshold Slope (SS) with high Ion/Ioff ratio. It also provides good thermal stability as compared to SELBOX-JLT. The Fringe capacitance of SELBOX-CPJLT MOSFET has also been tabulated for different device parameters using conformal mapping technique. The proposed device is simulated and validated by using 2D-Silvaco (ATLAS) simulation.

Analysis of Intrinsic Switching Losses in Superjunction MOSFETs Under Zero Voltage Switching

Switching losses of power transistors usually are the most relevant energy losses in high-frequency power converters. Soft-switching techniques allow a reduction of these losses, but even under soft-switching conditions, these losses can be significant, especially at light load and very high switching frequency. In this paper, hysteresis and energy losses are shown during the charge and discharge of the output capacitance (COSS) of commercial high voltage Superjunction MOSFETs. Moreover, a simple methodology to include information about these two phenomena in datasheets using a commercial system is suggested to manufacturers. Simulation models including COSS hysteresis and a figure of merit considering these intrinsic energy losses are also proposed. Simulation and experimental measurements using an LLC resonant converter have been performed to validate the proposed mechanism and the usefulness of the proposed simulation models.

Measurement of Power Dissipation Due to Parasitic Capacitances of Power MOSFETs

Analysis of the switching losses in a power MOSFET is crucial for the design of efficient power electronic systems. Currently, the state-of-the-art technique is based on measured drain current and drain-to-source voltage during the switching intervals. However, this technique does not separate the switching power due to the resistance of the MOSFET channel and due to the parasitic capacitances. In this paper, we propose a measurement method to extract the power dissipation due to the parasitic capacitances of a MOSFET, providing useful information for device selection and for the design of efficient power electronic systems. The proposed method is demonstrated on a basic boost converter. The proposed method shows that the existing method underestimates the turn-On losses by 41% and overestimates the turn-Off losses by 35%.

Non-Linear Capacitance of Si SJ MOSFETs in Resonant Zero Voltage Switching Applications

The parasitic capacitances of modern Si SJ MOSFETs are characterized by their non-linearity. At high voltages the total stored energy Eoss(VDC) in the output capacitance Coss(v) differs substantially from the energy in an equivalent linear capacitor Coss(tr) storing the same amount of charge. That difference requires the definition of an additional equivalent linear capacitor Coss(er) storing the same amount of energy at a specific voltage. However, the parasitic capacitances of current SiC and GaN devices have a more linear distribution of charge along the voltage. Moreover, the equivalent Coss(tr) and Coss(er) of SiC and GaN devices are smaller than the ones of a Si device with a similar Rds,on. In this work, the impact of the non-linear distribution of charge in the performance and the design of resonant ZVS converters is analyzed. A Si SJ device is compared to a SiC device of equivalent Coss(tr), and to a GaN device of equivalent Coss(er), in single device topologies and half-bridge based topologies, in full ZVS and in partial or full hard-switching. A prototype of 3300 W resonant LLC DCDC converter, with nominal 400 V input to 52 V output, was designed and built to demonstrate the validity of the analysis.

Modeling and Implementation of Optimal Asymmetric Variable Dead-Time Setting for SiC MOSFET-Based Three-Phase Two-Level Inverters

Efficiency, power quality, and reliability of SiC MOSFET-based voltage-source converters are significantly affected by the dead-time settings. The conventional fixed dead-time setting can induce large output voltage loss and additional energy loss due to the output capacitance of the SiC MOSFETs and the SiC Schottky barrier diodes or the freewheeling of the diodes, which will be more serious under high switching frequencies. This paper analyzes and models the detailed switching process of the SiC MOSFET half-bridge circuit when various dead-time settings are adopted. Based on the models, an optimal asymmetric variable dead-time (OAVDT) setting is proposed, which can avoid the discharging loss of the output capacitance and redundant freewheeling loss of the diode. The OAVDT setting is realized by adjusting the optimal dead-time in real time after the active device is turned off , which does not require any additional hardware circuits. The OAVDT setting can also reduce the output voltage loss to a certain level compared to the fixed dead-time setting. A three-phase two-level SiC MOSFET inverter has been built in the lab to verify the proposed OAVDT setting. Experimental results show a decrease of power loss by 22.5% with reduced output voltage loss compared to the fixed dead-time setting of 0.28 μs when the output power is 8 kW and the switching frequency is 40 kHz. The proposed OAVDT setting shows clear advantages over that of fixed dead-time setting, especially at light load and high switching frequencies.

High Off-State Impedance Gate Driver of SiC MOSFETs for Crosstalk Voltage Elimination Considering Common-Source Inductance

The crosstalk voltage on the gate-source terminal of SiC power mosfets in a phase-leg circuit is composed of the gate-drain capacitor introduced voltage and the common-source inductor introduced voltage. The mathematical model of the crosstalk voltage indicates that to suppress two types of crosstalk voltage, there exists a contradictory requirement on the off-state gate loop impedance. This challenge reduces the effectiveness of conventional crosstalk elimination methods. As an improvement, a crosstalk voltage suppression circuit that synchronously eliminates the crosstalk voltage of gate-drain capacitance and the common-source inductance is proposed. In this article, instead of creating low-impedance gate loop in the off-state, a high-impedance gate loop is formatted to eliminate the voltage drop on the common-source inductance. Meanwhile, the potential false turn-on or the negative voltage spikes caused by gate-drain capacitance is eliminated by the precharge voltage in the gate-source capacitor. The required prestored charge is analyzed considering the nonlinear behavior of the junction capacitance of the SiC mosfets. The proposed gate driver is experimentally verified in different switching conditions.

Impact of gamma-ray irradiation on dynamic characteristics of Si and SiC power MOSFETs

Power electronic devices in spacecraft and military applications requires high radiation tolerant. The semiconductor devices face the issue of device degradation due to their sensitivity to radiation. Power MOSFET is one of the primary components of these power electronic devices because of its capabilities of fast switching speed and low power consumption. These abilities are challenged by ionizing radiation which damages the devices by inducing charge built-up in the sensitive oxide layer of power MOSFET. Radiations degrade the oxides in a power MOSFET through Total Ionization Dose effect mechanism that creates defects by generation of excessive electron–hole pairs causing electrical characteristics shifts. This study investigates the impact of gamma ray irradiation on dynamic characteristics of silicon and silicon carbide power MOSFET. The switching speed is limit at the higher doses due to the increase capacitance in power MOSFETs. Thus, the power circuit may operate improper due to the switching speed has changed by increasing or decreasing capacitances in power MOSFETs. These defects are obtained due to the penetration of Cobalt60 gamma ray dose level from 50krad to 600krad. The irradiated devices were evaluated through its shifts in the capacitance-voltage characteristics, results were analyzed and plotted for the both silicon and silicon carbide power MOSFET.

Analysis and Modeling of Inner Fringing Field Effect on Negative Capacitance FinFETs

We investigate the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node. The 8-/7-nm technology node of the p-type body NC-FinFET is modeled using the Sentaurus technology-aided design (TCAD), which couples Poisson with Landau equations. It is found that the NC effect is beneficial for device scaling. The OFF current is well suppressed in short-channel devices (64.4% reduction at LG = 16 nm) because the inner fringing field induces negative gate charges and decreases the channel potential. For longer channel devices, the influence of inner fringing field disappears, and the depletion charges dominate the subthreshold characteristics. As reducing remnant polarization, the ON current is boosted (11.4% improvement at LG = 16 nm) for all lengths due to better matching between MOSFET and ferroelectric capacitances. In comparison with FinFET, the drain-induced barrier lowering of NC-FinFET is also well controlled (50% reduction at LG = 16 nm) due to the inner fringing field-induced gate charges, showing the scaling capability of NC-FinFET. Furthermore, a compact model to capture the spatial distribution of the inner fringing field is also proposed based on the Gaussian quadrature method, and it is validated with the TCAD simulated data with multiple gate lengths and remnant polarizations.

Analytical Switching Loss Modeling Based on Datasheet Parameters for &lt;sc&gt;mosfet&lt;/sc&gt;s in a Half-Bridge

Modern wide-bandgap devices, such as SiC- or GaN-based devices, feature significantly reduced switching losses, and the question arises if soft-switching operating modes are still beneficial. For most of the semiconductor devices, only limited information is available to estimate the switching losses. Especially, if a wide operating range is desired, excessive measurements have to be performed to determine the switching losses for arbitrary operating points. Therefore, in this paper, a fast calculation method to determine the switching losses based on the charge equivalent approximation of the mosfet capacitances, relying only on datasheet parameters, is presented. In addition, the turn- off losses at high switching currents are investigated, and an analytical expression to estimate the maximum current range for which the mosfet can be turned off with negligible switching losses is proposed.

Transient negative capacitance and charge trapping in FDSOI MOSFETs with ferroelectric HfYOX

Steep slope negative capacitance MOSFETs with HfYOx ferroelectric on FDSOI were experimentally demonstrated. An average SS of 30 mV/dec was achieved over 3 decades of drain current. The negative capacitance is believed to be a transient phenomenon because a strong polarization switching is needed for the steep slope. We found that the sub-thermal SS degrades with the cycling measurements, which is assumed to be caused by the trap charging in the ferroelectric oxide layer. The tradeoff between polarization and charge trapping is responsible for the subthreshold behavior of the device.

A Simple SR Gate Driving Circuit With Reduced Gate Driving Loss for Phase-Shifted Full-Bridge Converter

The phase-shifted full-bridge (PSFB) converter with synchronous rectifier (SR) is one of the most attractive dc–dc converters for the server power supply due to its high power capability and small secondary ripple current with the output inductor. Moreover, it can more reduce the secondary conduction loss by using parallel-connected mosfet s in SR. However, due to large input capacitance of the parallel-connected mosfet s in SR, the PSFB converter has large SR gate driving loss, which particularly degrades the light load efficiency. Thus, in this paper, one additional resistor is added to the conventional SR gate driving circuit to recycle the gate driving energy. As a result, the proposed circuit can improve the light load efficiency of the PSFB converter without operation mode change, additional controls, and complex circuits. The most advantage of the proposed circuit is that it is very simple and available to any other SR gate driver IC. The validity of the proposed circuit is confirmed by experimental results from a prototype with 340–400 V input and 12 V/66.66 A output.