Modeling and Implementation of Optimal Asymmetric Variable Dead-Time Setting for SiC MOSFET-Based Three-Phase Two-Level Inverters

Abstract

Efficiency, power quality, and reliability of SiC MOSFET-based voltage-source converters are significantly affected by the dead-time settings. The conventional fixed dead-time setting can induce large output voltage loss and additional energy loss due to the output capacitance of the SiC MOSFETs and the SiC Schottky barrier diodes or the freewheeling of the diodes, which will be more serious under high switching frequencies. This paper analyzes and models the detailed switching process of the SiC MOSFET half-bridge circuit when various dead-time settings are adopted. Based on the models, an optimal asymmetric variable dead-time (OAVDT) setting is proposed, which can avoid the discharging loss of the output capacitance and redundant freewheeling loss of the diode. The OAVDT setting is realized by adjusting the optimal dead-time in real time after the active device is turned off , which does not require any additional hardware circuits. The OAVDT setting can also reduce the output voltage loss to a certain level compared to the fixed dead-time setting. A three-phase two-level SiC MOSFET inverter has been built in the lab to verify the proposed OAVDT setting. Experimental results show a decrease of power loss by 22.5% with reduced output voltage loss compared to the fixed dead-time setting of 0.28 μs when the output power is 8 kW and the switching frequency is 40 kHz. The proposed OAVDT setting shows clear advantages over that of fixed dead-time setting, especially at light load and high switching frequencies.