Cancellation Circuit Research Articles

Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators

Transient performance is one of the most crucial design properties in digital low-dropout regulator (DLDO) design. In this paper, an improved droop measurement built-in self-test (BIST) circuit for DLDOs is presented, expanding on the previous work (Dirican et al. 2018) by the same authors. The proposed BIST system can detect and store the transient droop information using droop detector and generates a digital output with a reuse based 10-bit successive-approximation (SAR) analog-to-digital converter (ADC) with better accuracy. The improvements are achieved by employing a multi-step ramp circuit and a leakage cancellation circuit. The system is made more suitable for process scaling by replacing the analog buffer with a multi-step ramp circuit. Employing a leakage cancellation circuit solves potential leakage problems during ADC operation due to the reused decoupling capacitor of the DLDO and nearly 75% reduction in maximum measurement error is observed using this feature. Additionally, the droop detector is capable of storing transient droop information with less than 0.6% error for droop voltages ranging from 45 mV to 406 mV for a nominal DLDO output voltage of 1.6 V where the supply voltage is 1.8 V. The proposed BIST circuit is designed using a 0.18 μm CMOS process in Cadence Virtuoso and verified with corner simulations.

A rail‐to‐rail low‐power latch comparator with time domain bulk‐tuned offset cancellation for low‐voltage applications

SummaryLow‐voltage high‐precision comparators are the main building blocks of many low‐power mixed‐mode electronic devices. In this paper, a rail‐to‐rail high‐precision comparator is introduced. The proposed comparator uses 2 parallel input P‐type metal‐oxide‐semiconductor pairs with a dynamic level shifter to ensure rail‐to‐rail operation. Moreover, the proposed circuit incorporates a rail‐to‐rail offset cancellation circuit. The offset cancellation circuit works based on a time domain bulk‐tuned negative feedback loop. The proposed comparator and offset cancellation circuits are designed to work correctly when the input common mode voltage varies from rail to rail. The rail‐to‐rail scheme allows the use of the proposed comparator in nanometer technologies, where the acceptable input range is limited. The proposed circuit was simulated in a standard 180 nm complementary metal‐oxide‐semiconductor technology, and the results proved the rail‐to‐rail comparison ability in addition to the rail‐to‐rail offset cancellation function. The overall power consumption of the comparator was only increased by 11% compared with the conventional non–rail‐to‐rail approach. The maximum clock frequency of the proposed circuit is 833 MHz, which is slightly more than its counterpart at similar operation conditions.

Design of a constant-bandwidth variable-gain amplifier for LTE receivers

In this study, a constant-bandwidth variable-gain amplifier (VGA) is presented for long-term evolution (LTE) receivers. The presented VGA’s description is given with a newly proposed exponential-current generator, and also the common-mode feedback and the DC-offset cancellation (DCOC) circuits. The proposed exponential current generator is based on the Taylor series approximation in such a way that it can be expanded to meet the required gain control range. The simulations are performed using the TSMC 180 nm process technology with Cadence Analog Virtuoso. The VGA has a 45 dB gain control range, 180 MHz bandwidth, 15.7 dB m the third-order input-intercept point for minimum gain and below 20 dB noise figure for maximum gain which makes it convenient for LTE receivers. The simulations also show that the bandwidth of the VGA is fairly constant over the control range. Monte Carlo simulations reveal that by using a DCOC circuit, the VGA provides 30 dB output offset rejection. The overall power consumption of the circuit is 9.1 mW under a 1.8 V power supply.

Phase noise analysis of proposed PFD and CP switching circuit and its advantages over various PFD/CP switching circuits in phase-locked loops

This paper presents the design of a new phase frequency detector (PFD) and different type of charge pump (CP) circuits for phase-locked loops. A proposed phase frequency detector circuit can eliminate the effect of missing edge and phase ambiguity problems in many PFDs. A novel CP circuit with a special switching scheme has been incorporated to reduce the current mismatch error, charge injection error and clock feed through effect in many CP circuits using a new and unique clocking scheme of up delay (UPD) and down bar-delay (DNBD) signals in place of the conventional UPD and DNB clock pulses. Output noise, input referred phase noise, and phase noise performance (with 10 fF load capacitance) of the proposed PFD and true single phase clock (TSPC) PFD have been studied with different CP circuits. The effect of CP current mismatch and DC offset current at any of the current source or sink has been incorporated to check the effect on spur and phase noise performance of the ΔΣ fractional-N PLL frequency synthesizer. In addition, PFD and charge pump circuit phase noise estimation theory has been illustrated and it has been verified through the transistor level simulation. PLL locking response has been verified through the transistor level simulation in Cadence SpectreRF for the different CPs configuration with the proposed PFD and it shows that the proposed PFD and different CP circuits lock much faster than other works in literature. This condition also holds for the automatic frequency control unit along with the loop bandwidth calibration circuit and in special case of both loop bandwidth calibration and phase noise cancellation circuit. According to our knowledge this work shows a new state of the art performances for this proposed charge pump circuit and phase noise analysis of the charge pump circuit in presence of an error amplifier and many switching circuits.

Self‐interference cancellations for full‐duplex RF front‐end using a broadband phase‐slope adjuster

AbstractWith improved wide‐band performances compared to classical RF signal cancellation circuits, an alternate self‐interference cancellation method is presented for a full‐duplex front‐end involving a phase‐slope adjuster. This solution can adapt frequency‐dependent phase mismatch in the cancellation path. This adjuster consists of a hybrid coupler and two varactor diodes, which can expand a single cancellation sweet spot to a continuous frequency range because of a newly introduced fine phase slope tuning capability. From measurement results, a single‐loop demo circuit can suppress interferences by 42 and 32 dB in 20 and 60 MHz bandwidth, respectively.

Wideband RF Self-Interference Cancellation Circuit for Phased Array Simultaneous Transmit and Receive Systems

With the growing demand for spectrum utilization, the concept of full duplex transceivers has become attractive. These simultaneous transmit and receive systems (STAR) are attractive as they double bandwidth utilization. To realize STAR, we must suppress self-interference (SI) between transmit and receive antennas. Doing this across a wide bandwidth presents an even greater challenge. Further, for antenna arrays, SI can be higher due to mutual coupling among neighboring elements. In this paper, we achieve 100 dB isolation for practical STAR, across a large 500 MHz bandwidth. Specifically, four stages of the self-interference cancellation are proposed. In addition to high isolation cross-polarized array elements, we employ multi-tap filters at the transceiver RF front-end for interference cancellation. These filters emulate direct SI coupling using frequency-domain optimization techniques. Measured results show an average of 25 dB filter cancellation is possible across 500 MHz.

An EMI-Resistant Common-Mode Cancelation Differential Input Stage in UMC 180 nm CMOS

This letter presents an on-chip common-mode cancelation circuit (CMCC), which increases the immunity to electromagnetic interference (EMI) of the input stage in a classic CMOS operational amplifier. Two test chips, containing a classic Miller amplifier and a Miller amplifier with CMCC, respectively, have been fabricated in the UMC 180 nm CMOS process. Measurements illustrate how the latter amplifier exhibits an increased immunity to EMI compared with the former.

Dual-Polarized, Differential Fed Microstrip Patch Antennas With Very High Interport Isolation for Full-Duplex Communication

This communication presents two dual-polarized microstrip patch antenna systems based on a single radiating element with 180° ring hybrid coupler for differential feeding to achieve high interport RF isolation. One of the implemented single-layer patch antennas provides more than 67 dB isolation between transmit (Tx) and receive (Rx) ports at 2.4 GHz while the second fabricated antenna with slot coupled Tx port along with differential feeding for Rx operation provides more than 90 dB RF isolation at 2.41 GHz between dc isolated Tx–Rx ports. Moreover, the single-layer antenna provides better than 62 dB interport isolation for 10 dB-return loss impedance bandwidth (BW) of 50 MHz. Measured interport isolation for implemented antenna with slot coupled Tx port achieves around 70 and 79 dB port to port RF isolation for 50 and 20 MHz BWs, respectively, and these are the highest amounts of isolation for a single antenna to best of our knowledge. The antenna with slot coupled Tx port provides more interport RF isolation as compared to single-layer antenna due to low coupling between slot coupled and co-planar quarter-wave microstrip fed ports. Both antenna structures have the capability to remove in-band nonlinear self-interference (SI) components without complex SI cancellation circuits.

Improved soft-switching boost converter with coupled-inductor using passive EMI cancellation method

Non-isolated switching power supplies with coupled-inductor have more parasitic elements like the leakage inductance in comparison with the regular non-isolated converters. Due to the undesirable resonances between the leakage inductance and other parasitic capacitors, the conducted electromagnetic emissions increase. In order to improve electromagnetic compatibility, adopting passive or active parasitic cancellation methods can be used. In this paper, a passive cancellation circuit is combined with the converter`s coupled-inductor cell. Among the non-isolated converters, the boost converter where a lossless snubber with a coupled inductor is applied in its soft switching cell is selected to reveal the advantage of this proposed method with respect to EMC. To verify the advantage, the conducted EMI of this proposed converter is compared with the regular boost converter and boost converter with a lossless snubber. The experimental results indicate a considerable reduction in the conducted EMI levels. This proposed technique can be applied in other non-isolated topologies like buck, buck-boost, SEPIC, Ćuk and converters with tapped inductor.

Coupled-Inductor-Based High-Step-Down-Ratio Converter with Output Current Ripple Reduction

Even though the coupled-inductor-based high-step-down-ratio converters can achieve a higher step-down voltage gain than the traditional buck converter, their output current suffer from a high output current ripple, causing a high output voltage ripple. Therefore, a bulky electrolytic output capacitor is usually used to suppress the output voltage ripple. Moreover, the longevity of the output electrolytic capacitor is highly dependent on the output current ripple. In [6–8], a passive current ripple cancellation circuit was applied to the DC–DC converters to reduce the output current ripple. However, these literatures did not mention and analyze the situations for coupled-inductor converters. Moreover, the same concept, including analysis and design, cannot be directly applied to the coupled-inductor-based converters. Therefore, in this paper, the analysis, design, and experimental results of the current ripple cancellation circuit applied to the coupled-inductor-based high-step-down-ratio converter are given to verify the effectiveness.

Digital Pre-Distortion of Carrier Frequency Offset for Reliable Wi-Fi Enabled IoTs

The Internet of Things (IoTs) will change the requirements for wireless connectivity significantly, mainly with regard to service coverage, data rate, and energy efficiency. Therefore, to improve robustness and reliability, WiFi-enabled IoT devices have been developed to use narrowband communication. However, narrowband transmission in WiFi such as IEEE 802.11ah causes relatively higher frequency error due to the reduced subcarrier space, which is larger than legacy wireless local area networks (WLANs) in 2.4/5 GHz frequencies. In a direct conversion receiver, this error degrades the signal quality due to the presence of direct current (DC) offset cancellation circuits. In this paper, a digital carrier frequency offset (CFO) predistortion scheme is proposed for a reliable communication link in dense networks. Evaluation results demonstrate that the proposed scheme can improve received signal quality in terms of packet error rate and error vector magnitude.

Analysis and Design of Integrated Active Cancellation Transceiver for Frequency Division Duplex Systems

An active transmitter (TX) cancellation scheme enabling integration of the antenna interface for frequency division duplex systems is presented. A replica of the TX current is synthesized in shunt with the receiver (RX) by a digital-to-analog converter (DAC). The replica DAC virtually shorts out the TX signal at the RX input while having minimal impact on the TX insertion loss. Propagation of the TX phase noise in the RX band is analyzed and shown to be feed-forward cancelled in the proposed system. A prototype chip including integrated TX, measurement RX, and cancellation circuits, operating on a single-shared antenna, is implemented in 65-nm CMOS. The cancellation replica demonstrates > 50 dB cancellation of a +12.6 dBm peak 20-MHz TX signal across a wide range of center frequencies and up to 5:1 voltage standing-wave ratio at the antenna interface. The RX is able to down-convert the RX signal at 40-MHz offset with < 4.3 dB noise figure degradation in the presence of the residual TX signal.

A new high-speed low-power and low-offset dynamic comparator with a current-mode offset compensation technique

In this paper a new low-power high-speed offset-compensated dynamic latched comparator is presented. The proposed comparator uses a two-stage charge-steering preamplifier to achieve high pre-amplification voltage gain. Higher input voltage range of the latch stage significantly reduces the delay time of the latch and relaxes the need for high current in the regeneration process which ensures low-power structure. In addition, a new digitally controlled offset cancellation circuit based on the current-steering structure is used to reduce the offset of comparator. Offset voltage reduction in the startup time is the key advantage of the proposed calibration technique which does not require refreshing the offset cancellation process. Post-layout simulation results in 0.18µm standard TSMC CMOS process show that the designed comparator dissipates 135µW of power consumption from a 1.2V supply voltage and has the 1mV accuracy while operating at 1GHz clock frequency. The power and delay time of the proposed comparator are less than about 10% of the new state-of-the-art comparator. Furthermore, from the Monte-Carlo analysis, the standard deviation of the input referred offset voltage in typical process corner and temperature is obtained about 17.53/1.09mV before and after offset cancellation, respectively.

Input-Current-Ripple-Free Two-Channel LED Driver

In this paper, an input-current-ripple-free two-channel light-emitting diode (LED) driver is presented. In the proposed LED driver, a current-sharing capacitor is integrated into the boost converter to achieve the current-sharing among the LEDs and to enhance the output voltage gain. Moreover, an input current ripple cancellation circuit is employed to eliminate the input current ripple. Finally, the operating principle, analysis, and experimental results are provided to verify the effectiveness of the proposed LED driver.

A 10-GHz Delay Line Frequency Discriminator and PD/CP-Based CMOS Phase Noise Measurement Circuit

This paper presents a delay line frequency discriminator and phase detector/charge pump (PD/CP)-based phase noise measurement (PNM) circuit with wide bandwidth, great sensitivity, and reliable on-chip integration. A delay-locked loop is integrated to automatically align the PD input phases, and a dc offset cancellation circuit is embedded to overcome the circuit mismatches. This PNM demonstrates −61/−81 dBc single tone sensitivity and −110.35/−138.60 dBc/Hz phase noise sensitivity at 100 kHz/1 MHz-offset, respectively, for a 10-GHz clock. The PNM errors are 0.35/1.12 dB at 100 kHz/1 MHz, respectively, compared with the signal analyzer’s (Agilent N9030A) PNM results. The PNM bandwidth is 110 MHz. This proof-of-concept design is fabricated in a 65-nm CMOS technology with the chip area of 1.5 mm $\times1.3$ mm. The circuit consumes 97.7 mW of power.

Current‐balance method for multi‐phase DC–DC buck converters with wide duty ratio applications in both CCM and DCM

To cope with the current imbalance situation of multi-phase buck converters with wide duty ratio range applications in continuous conduction mode (CCM) and discontinuous conduction mode (DCM), a current-balance method is proposed. In CCM, with small power loss, current balance can be achieved by comparing the replica currents flowing through the sensing transistors. In DCM, an additional offset cancellation circuit is designed to eliminate the intrinsic offset voltage mismatch existing in main-loop comparators. Then each phase sequentially performs a switching operation to share the switching stress. Experimental results show that the current imbalance is decreased to 0.15% under duty ratio from 0.1 to 0.75. Load current is well distributed between phases in both the CCM and DCM without tricky implement.

低温poly-Si TFT-LCDドライバ用オフセットキャンセラー

低温poly-Si TFT-LCDドライバ用オフセットキャンセラー

Self-interference suppression improvement by employing circular polarized antennas

This paper presents a novel method for suppressing the self-interference due to multipath in WiFi nodes of full-duplex systems based on employing two circular polarized antennas. Three different techniques have been used in order to suppress the interference generated by the direct wave: antenna separation, antenna pattern and analogue cancellation circuit comprised of a balun, a phase shifter and a variable attenuator. As a result, an initial isolation of 90dB was achieved inside an anechoic chamber. In order to beat the multipath interference circular polarization was employed. With the aim of analyzing the robustness of the circular polarization in comparison with the linear one, the self-interference between transmitter and receiver was measured in nine different environments. The measured level of self-interference was also compared with the results achieved inside the anechoic chamber. In this way, the degradation of the self-interference suppression due to multipath was evaluated. Results show better isolation when employing circularly polarized antennas in seven of nine environments. In addition, with the circular polarization self-interference suppression higher than 70dB was achieved independently of the environment.

A fast, low power and low noise charge sensitive amplifier ASIC for a UV imaging single photon detector

NASA has funded, through their Strategic Astrophysics Technology (SAT) program, the development of a cross strip (XS) microchannel plate (MCP) detector with the intention to increase its technology readiness level (TRL), enabling prototyping for future NASA missions. One aspect of the development is to convert the large and high powered laboratory Parallel Cross Strip (PXS) readout electronics into application specific integrated circuits (ASICs) to decrease their mass, volume, and power consumption (all limited resources in space) and to make them more robust to the environments of rocket launch and space. The redesign also foresees to increase the overall readout event rate, and decrease the noise contribution of the readout system. This work presents the design and verification of the first stage for the new readout system, the 16 channel charge sensitive amplifier ASIC, called the CSAv3. The single channel amplifier is composed of a charge sensitive amplifier (pre-amplifier), a pole zero cancellation circuit and a shaping amplifier. An additional output stage buffer allows polarity selection of the output analog signal. The operation of the amplifier is programmable via serial bus. It provides an equivalent noise charge (ENC) of around 600 e^− and a baseline gain of 10 mV/fC. The full scale pulse shaped output signal is confined within 100 ns, without long recovery tails, enabling up to 10 MHz periodic event rates without signal pile up. This ASIC was designed and fabricated in 130 nm, TSMC CMOS 1.2 V technology. In addition, we briefly discuss the construction of the readout system and plans for the future work.

Common-mode noise cancellation circuit for wearable ECG.

Wearable electrocardiogram (ECG) is attracting much attention for monitoring heart diseases in healthcare and medical applications. However, an imbalance usually exists between the contact resistances of sensing electrodes, so that a common mode noise caused by external electromagnetic field can be converted into the ECG detection circuit as a differential mode interference voltage. In this study, after explaining the mechanism of how the common mode noise is converted to a differential mode interference voltage, the authors propose a circuit with cadmium sulphide photo-resistors for cancelling the imbalance between the contact resistances and confirm its validity by simulation experiment. As a result, the authors found that the interference voltage generated at the wearable ECG can be effectively reduced to a sufficient small level.