Phase noise analysis of proposed PFD and CP switching circuit and its advantages over various PFD/CP switching circuits in phase-locked loops

Abstract

This paper presents the design of a new phase frequency detector (PFD) and different type of charge pump (CP) circuits for phase-locked loops. A proposed phase frequency detector circuit can eliminate the effect of missing edge and phase ambiguity problems in many PFDs. A novel CP circuit with a special switching scheme has been incorporated to reduce the current mismatch error, charge injection error and clock feed through effect in many CP circuits using a new and unique clocking scheme of up delay (UPD) and down bar-delay (DNBD) signals in place of the conventional UPD and DNB clock pulses. Output noise, input referred phase noise, and phase noise performance (with 10 fF load capacitance) of the proposed PFD and true single phase clock (TSPC) PFD have been studied with different CP circuits. The effect of CP current mismatch and DC offset current at any of the current source or sink has been incorporated to check the effect on spur and phase noise performance of the ΔΣ fractional-N PLL frequency synthesizer. In addition, PFD and charge pump circuit phase noise estimation theory has been illustrated and it has been verified through the transistor level simulation. PLL locking response has been verified through the transistor level simulation in Cadence SpectreRF for the different CPs configuration with the proposed PFD and it shows that the proposed PFD and different CP circuits lock much faster than other works in literature. This condition also holds for the automatic frequency control unit along with the loop bandwidth calibration circuit and in special case of both loop bandwidth calibration and phase noise cancellation circuit. According to our knowledge this work shows a new state of the art performances for this proposed charge pump circuit and phase noise analysis of the charge pump circuit in presence of an error amplifier and many switching circuits.