A 10-GHz Delay Line Frequency Discriminator and PD/CP-Based CMOS Phase Noise Measurement Circuit

Abstract

This paper presents a delay line frequency discriminator and phase detector/charge pump (PD/CP)-based phase noise measurement (PNM) circuit with wide bandwidth, great sensitivity, and reliable on-chip integration. A delay-locked loop is integrated to automatically align the PD input phases, and a dc offset cancellation circuit is embedded to overcome the circuit mismatches. This PNM demonstrates −61/−81 dBc single tone sensitivity and −110.35/−138.60 dBc/Hz phase noise sensitivity at 100 kHz/1 MHz-offset, respectively, for a 10-GHz clock. The PNM errors are 0.35/1.12 dB at 100 kHz/1 MHz, respectively, compared with the signal analyzer’s (Agilent N9030A) PNM results. The PNM bandwidth is 110 MHz. This proof-of-concept design is fabricated in a 65-nm CMOS technology with the chip area of 1.5 mm $\times1.3$ mm. The circuit consumes 97.7 mW of power.