Cancellation Circuit Research Articles

Enabling data-driven and bidirectional model development in Verilog-A for photonic devices

We present a method to model photonic components in Verilog-A by introducing bidirectional signaling through a single port. To achieve this, the concept of power waves and scattering parameters from electromagnetism are employed. As a consequence, one can simultaneously transmit forward and backward propagating waves on a single wire while also capturing realistic, measurement-backed responses of photonic components in Verilog-A. We demonstrate examples to show the efficacy of the proposed technique in accounting for critical effects in photonic integrated circuits such as Fabry-Perot cavity resonance, reflections to lasers, reflection cancellation circuits, etc. Our solution makes electronic-photonic co-simulation more intuitive and accurate.

Johnson-noise-limited cancellation-free microwave impedance microscopy with monolithic silicon cantilever probes

Microwave impedance microscopy (MIM) is an emerging scanning probe technique for nanoscale complex permittivity mapping and has made significant impacts in diverse fields. To date, the most significant hurdles that limit its widespread use are the requirements of specialized microwave probes and high-precision cancellation circuits. Here, we show that forgoing both elements not only is feasible but also enhances performance. Using monolithic silicon cantilever probes and a cancellation-free architecture, we demonstrate Johnson-noise-limited, drift-free MIM operation with 15 nm spatial resolution, minimal topography crosstalk, and an unprecedented sensitivity of 0.26 zF/√Hz. We accomplish this by taking advantage of the high mechanical resonant frequency and spatial resolution of silicon probes, the inherent common-mode phase noise rejection of self-referenced homodyne detection, and the exceptional stability of the streamlined architecture. Our approach makes MIM drastically more accessible and paves the way for advanced operation modes as well as integration with complementary techniques.

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs).

Fully Integrated 24-GHz 1TX-2RX Transceiver for Compact FMCW Radar Applications.

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is -80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm2 die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

Feedthrough effect in MEMS gyroscopes and fully differential feedthrough cancellation method.

In the operation of MEMS gyroscopes, the feedthrough signal is inevitably introduced through the feedthrough capacitance and significantly affects the performance of MEMS gyroscopes. The common feedthrough cancellation methods highly depend on the microfabrication process and the structural symmetry of MEMS gyroscopes, which cannot effectively eliminate the feedthrough signal. In order to solve this problem, a new feedthrough cancellation method based on a fully differential configuration is proposed in this paper. The influence of the feedthrough effect is analyzed by establishing an equivalent circuit model including the feedthrough capacitance and described by the admittance diagram. Different drive and detection configurations are compared for the problem of feedthrough mismatch on different paths. Based on the theoretical analysis, a fully differential feedthrough cancellation scheme combined with two inverse feedthrough cancellation circuits is proposed. The deviation of feedthrough signal caused by the asymmetry of two differential paths can be adjusted by the two inverse feedthrough cancellation circuits. The fully differential configuration can further increase the drive force and suppress the common mode errors. The experimental results indicate that the feedthrough signal is suppressed in a large degree by the designed feedthrough cancellation method. The feedthrough level is reduced by 50.53 dB, and the amplitude of the effective signal increases from 4.10 to 9.46 dB. The signal-to-noise ratio has an improvement of 212.48% than that before feedthrough cancellation. The proposed feedthrough cancellation method can significantly reduce the interference of feedthrough signals on the effective signal, effectively improving the signal quality of MEMS gyroscopes.

LIFETIME PREDICTION OF SINGLE-STAGE LED DRIVER CIRCUIT USING BAYESIAN BELIEF NETWORK

In light-emitting diode (LED) lighting, the driver commands the lifetime and the LED bulb. It is essential to predict the driver's lifetime during its design stage. This paper proposes a viable method to predict the lifetime of the LED driver based on its failure rate. A novel single-ended primary inductor converter (SEPIC) integrated parallel ripple cancellation circuit (PRC) topology of 30 W is considered to estimate the lifetime of the driver circuit. The failure rate model is regarded as a base to predict the lifetime of LED drivers using Bayesian belief network (BBN) analysis. The weakest links are the prime components to estimate the lifetime, and they are active devices and capacitors employed in the driver circuit. The output capacitor is considered a degree of importance as per the existing literature, and the proposed course has been designed without using any electrolytic capacitor (EC) to enhance the reliability of the driver circuit. This approach ensures an effective way to access the mean time to failure (MTTF) or the lifetime of the LED driver in a lucrative manner.

An electronically tunable fractional order inductor employing VD-EXCCII

An electronically tunable Fractional Order Inductor (FOI) for both grounded as well as floating circuits is designed using a Voltage Differencing Extra-X Current Conveyor (VD-EXCCII), grounded MOS resistor, and grounded Fractional Order Capacitor (FOC) with four MOS switches. The grounded positive and negative fractional order functionality can be easily executed by using the gate voltage (VG) of an MOS transistor. Ideal as well as the non-ideal port characteristics of VD-EXCCII are also studied in the presence of the parasites available in the active block VD-EXCCII. The verification of the proposed FOI is first simulated through PSPICE in which the VD-EXCCII uses 0.18 μm TSMC CMOS parameter. In addition to traditional impedance verification of the proposed FOI, an application of the FOI is translated for the design of sixth order High-Pass Filter (HPF), sixth order Low-Pass Filter (LPF), and a voltage mode Multiple Input Single Output Universal Filter (MISO-UF) design. Moreover, the performance of the proposed negative FOI circuit is also demonstrated through a Fractional Inductance Cancellation Circuit (FICC).

A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery From Sleep Mode Under Voltage Drift

This brief presents a 10 Gb/s receiver for an application processor (AP)-to-timing controller-embedded display (TED) interface that is capable of recovering its operating frequency fast from the sleep mode under the supply voltage drift. A hybrid clock and data recovery (CDR) loop is employed to support the fast entering and exiting of the sleep mode by adding AND gates to the digital loop filter, while offering good jitter performance by utilizing an analog loop filter. Also supply voltage drift cancellation (SVDC) circuit is added to maintain constant current in the presence of supply voltage drift. Thanks to the hybrid CDR and SVDC, even if the supply voltage drift occurs during the sleep mode, the same frequency is recovered fast without frequency re-tracking. A prototype chip fabricated in 28-nm CMOS technology occupies an active area of 0.089mm2 with 0.99-pJ/bit energy efficiency in the active mode. The measured results show that the frequency is recovered within 36 ns even if the worst-case supply voltage drift occurs during the sleep mode.

A novel approach to interface high-Q Fabry–Pérot resonators with photonic circuits

The unique benefits of Fabry–Pérot resonators as frequency-stable reference cavities and as an efficient interface between atoms and photons make them an indispensable resource for emerging photonic technologies. To bring these performance benefits to next-generation communications, computation, and time-keeping systems, it will be necessary to develop strategies to integrate compact Fabry–Pérot resonators with photonic integrated circuits. In this paper, we demonstrate a novel reflection cancellation circuit that utilizes a numerically optimized multi-port polarization-splitting grating coupler to efficiently interface high-finesse Fabry–Pérot resonators with a silicon photonic circuit. This circuit interface produces a spatial separation of the incident and reflected waves, as required for on-chip Pound–Drever–Hall frequency locking, while also suppressing unwanted back reflections from the Fabry–Pérot resonator. Using inverse design principles, we design and fabricate a polarization-splitting grating coupler that achieves 55% coupling efficiency. This design realizes an insertion loss of 5.8 dB for the circuit interface and more than 9 dB of back reflection suppression, and we demonstrate the versatility of this system by using it to interface several reflective off-chip devices.

Dual-Photodiode Differential Receivers Achieving Double Photodetection Area for Gigabit-Per-Second Optical Wireless Communication

This article presents two dual-photodiode (PD) differential optical receivers that achieve double photodetection area to support gigabit-per-second optical wireless communication (OWC), while maintaining the receiver bandwidth. To enable differential light detection with a single incident light beam, a dual-PD OWC receiver architecture is proposed. In this architecture, two PDs are connected to the receiver complementarily without sacrificing the receiver bandwidth, and meanwhile, remain properly reversely biased. In addition, an adaptive dc photocurrent cancellation (ADPC) circuit is employed to prevent the saturation of the receivers under strong and imbalanced incident light. Based on the proposed architecture, two OWC receivers are implemented, including a proposed receiver and a reference one. In the proposed receiver, a low-noise shunt-feedback transimpedance amplifier (SF-TIA) with differential-pair-based current reuse and cross-coupled resistive feedback is proposed to enhance the sensitivity. In contrast, the reference receiver employs positive capacitive feedback to improve the transimpedance amplifier (TIA) performance. Both receivers have been fabricated with a standard 180 nm CMOS process and have been wire-bonded to two PDs. Experimental results indicate that both receivers can detect optical signals with data rates up to 2 Gb/s, and the proposed receiver architecture has significantly improved the bit error rate (BER) at 1.5 Gb/s from worse than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-6}$</tex-math> </inline-formula> –10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-9}$</tex-math> </inline-formula> (error-free) with constrained optical power density. Moreover, the proposed receiver achieves an input sensitivity of 3.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{pp}}$</tex-math> </inline-formula> due to the superior performance of the proposed TIA, which outperforms the sensitivity of 10.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{pp}}$</tex-math> </inline-formula> from the reference receiver. Both sensitivities are measured at 1.5 Gb/s for a BER of 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-9}$</tex-math> </inline-formula> (error-free). The power consumption of the proposed and the reference receiver are 24.3 and 19.1 mW, respectively, excluding the output driver.

Improving Isolation in Monostatic Simultaneous Transmit and Receive Systems Using a Quasi-Symmetrical Self-Interference Cancellation Architecture

For simultaneous transmit (Tx) and receive (Rx), it is a common practice, with monostatic full duplex (FD) systems, to use a single antenna and a circulator to provide isolation between the transmit and receive radio chains. However, most circulators currently on the market are designed to provide 12 to 20 dB of Tx/Rx port isolation, which is not sufficient for full duplex (FD) microwave communication. In fact, it is necessary to provide at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$&gt;$</tex-math></inline-formula> 30 dB of isolation to prevent the receiver desensitization that is caused by the leakage of high-power transmit signals. For this reason, practical simultaneous transmit and receive (STAR) systems require additional cancellation stages. In this paper, we present a novel STAR system that incorporates two circulators, a hybrid coupler, and a self-interference cancellation (SIC) circuit, based on a Finite Impulse Response (FIR) topology. Our design achieves an average Tx/Rx port isolation of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 37 dB over a 25 MHz bandwidth ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">viz.</i> 2.395–2.42 GHz) in simulation, with a minimum and maximum cancellations of 35 dB and 41 dB, respectively. A prototype was fabricated and tested showing good agreement with the simulations. All in all, the prototype achieved an average cancellation of 36 dB, with a cancellation range of 33 dB to 42 dB.

Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing

Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing

A 16-Channel Impedance-Readout IC With Synchronous Sampling and Baseline Cancelation for Fast Neural Electrical Impedance Tomography

Fast neural electrical impedance tomography (EIT) is a promising method to not only record neural activities but also to localize them in peripheral nerves in a minimally invasive way. A much higher image frame rate is required for this application than conventional impedance measurement applications, which generally adopt the I/Q demodulation technique. To achieve a high enough frame rate to capture neural activities along the peripheral nerve fascicle, this paper proposes synchronous sampling (SS) and fast baseline tracking based on successive approximation (SA). The SS method needs an injection of only a single or a few periods of square-wave current signal for the amplitude measurement by synchronously sampling the received voltage signal. The proposed SA-based baseline tracking provides fast signal recovery from unwanted motion artifacts or baseline drifts. The designed readout circuit uses a two-step conversion where its coarse bits are generated from a current-based baseline cancellation circuit and its fine bits from a following SAR ADC. Thanks to the baseline tracking based on the SS and SA, the proposed IC achieves a faster frame rate of 312 fps with continuous baseline update and 500 fps with constant baseline compared to state-of-the-art works. The implemented IC is validated by measuring a water-filled tank and reconstructing its tomographic image. The results show successful discrimination of varied impedance areas over the tank.

A 28 GHz RF-DAC With Analog LO Leakage Cancellation

A 28-GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 8$ </tex-math></inline-formula> bit quadrature RF-DAC is presented, which has an analog LO leakage cancellation circuit. It is based on a double-balanced Gilbert cell structure where current bleeding paths are introduced to prevent the cells from being completely turned off. LO leakages of the RF-DAC are canceled by controlling the current bleeding paths. It was fabricated in a 28-nm bulk CMOS process and achieved a −5.6-dBm CW output power with 12-mW power consumption from a 1.1 V supply and 3-Gb/s maximum data rate with 64-QAM signals. −45-dBc LO leakage was achieved using the proposed leakage cancellation technique.

Electronically tunable positive and negative fractional order inductor circuit using single topology

This article presents electronically tunable grounded and floating fractional order inductor circuits. The proposed circuits employ two operational transconductance amplifiers (OTAs), one fractional order capacitor, one inverter and four MOS switches and are capable to work in positive mode and negative mode without change in topology. The behaviour of the proposed circuit is also analyzed in presence of parasites that may appear in the practical circuit. The functional verification is done via pre and post layout simulations at 90 nm CMOS technology parameter. The usefulness of the proposed positive fractional inductor circuit is demonstrated through fractional order band pass filter and fractional order high pass ladder filter. The performance of the proposed negative fractional inductance circuit is demonstrated through a fractional inductance cancellation circuit.

Leakage-Current-Canceling Current-Sampling Sense Amplifier for Deep Submicrometer STT-RAM

In the design of nonvolatile memory (NVM), the sense amplifier (SA) contributes a major part of the power consumption due to high-frequency read operations. This brief proposes a leakage-current-canceling current-sampling sense amplifier (LCCS-SA) for the suppression of the read power consumption by operating in near-threshold region. The proposed LCCS-SA adopts the technology of offset cancellation and single-ended differential circuit structure to compensate the effect of the leakage current. The bit-line (BL) leakage-induced read failure is effectively suppressed in near-threshold region. Monte Carlo simulation demonstrates that the proposed LCCS-SA can operate at a supply voltage of 0.4 V and achieves 4.4 times lower read energy per bit compared to the conventional current-sampling-based SA.

A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing

This brief presents a 32-Gb/s PAM4-Binary bridge for the next-generation memory testing. The bridge incorporates all the required functions to evaluate a high-speed PAM4 memory using a low-speed NRZ tester. The low-speed data transmitted from the NRZ tester to the bridge are converted into high-speed PAM4 data through half-rate clock control and forwarded to the memory, and vice-versa. The ground-terminated PAM4 driver provides the single-ended output by controlling the output current with a 2-tap feed-forward equalizer, achieving a ratio level mismatch (RLM) of 0.95. To minimize the offset at the PAM4 receiver, the offset cancellation circuit with an offset of 2.76mV consisting of a CTLE and sampling latches is employed, and the horizontal margin of the received PAM4 signal is 50% for BER <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${ &lt; } 10^{-9}$ </tex-math></inline-formula> . An all-digital PLL integrated in the bridge doubles the 4-GHz WCK used as forwarded clock for the graphic memory. The count-based PAM4 eye-opening monitor is also proposed to find the optimal codes for the maximum eye opening using the PRBS7 data sequence. The bridge fabricated in the 40-nm CMOS technology occupies an active area of 1.6mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 132mW.

Maximizing Secondary Users’ Sum-Throughput in an In-Band Full-Duplex Cognitive Wireless Powered Backscatter Communication Network

This article studies the secondary users’ sum-throughput in an in-band full-duplex (I-FD) cognitive wireless powered backscatter communication network. The secondary network consists of a hybrid access point (H-AP) and a finite number of geographically distributed secondary backscatter sensors (SBSs), each capable of using either the conventional or backscatter communication. The secondary network shares the primary network’s spectrum using an underlay spectrum sharing model. In this model, the H-AP and SBSs operate in I-FD mode to achieve improved spectral and time efficiency. Moreover, when an SBS has little available energy, it switches to the low-energy consumption backscatter method instead of the conventional transmission method. The goal is to maximize the sum-throughput of the SBSs. It is shown that such a problem is a convex optimization problem. Closed-form expressions for the optimal allocated time and energy to SBSs are derived and solved via a low complexity and efficient algorithm called joint optimal time and energy allocation (JOTEA). Numerical results illustrate that the JOTEA algorithm achieves a higher sum-throughput than the benchmark equal time allocation method. Furthermore, if the self-interference cancellation circuit considerably cancels self-interference in the H-AP, the I-FD mode achieves a higher sum-throughput performance than that of the half-duplex mode. Moreover, using backscatter communication results in a further increase in the sum-throughput.

An Active EMI Cancellation Technique Achieving a 25-dB Reduction in Conducted EMI of LIN Drivers

Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state of the art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this paper an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics.

A Fully Integrated Passive Self-Jamming Cancellation Architecture with Fast Settling Time for UHF RFID Reader

This paper presents a fully integrated passive self-jamming cancellation (SJC) circuit in 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology for ultra-high frequency (UHF) radio frequency identification (RFID) applications. Based on the active amplitude and phase control, a novel passive variable capacitor array and signal combiner are adopted instead of a traditional variable amplifier/attenuator and a phase shifter to reduce the circuit complexity and thus achieve higher linearity and low noise. We use an improved cancellation algorithm based on the local search method to quickly and accurately find the cancellation point that minimizes the self-jamming signal power. The simulation and measurement results are constant, and a suppression of 38 dB can be achieved in the working frequency of 860–960 MHz. The cancellation algorithm can be finished within 0.5 ms. These results indicate that the designed SJC circuit can be a promising candidate for UHF RFID applications.