Camera Link Interface Research Articles

Design and Implementation of Airborne Hyperspectral Camera Control and Data Storage System

With the great progress of hyperspectral imaging technology, airborne hyperspectral cameras have been widely used in the field of earth detection and remote sensing. However, with the increasing resolution of airborne hyperspectral cameras, the amount of data acquired is also growing explosive, The speed and accuracy in the transmission process are easily affected, which poses challenges to the real-time control and data acquisition and storage of airborne hyperspectral cameras. In this paper, a general airborne hyperspectral image acquisition and storage system is designed, which converts the hyperspectral data from the Cameralink interface into a high-speed serial PCIe data stream and realizes high-speed storage of image data. The image width is 2048 pixels, the number of spectral segments is 120, the pixel size is 12bit, and the maximum frame rate is 300 fps. The maximum transmission rate is 2048×120×12bit×300fps, and the data rate is 844Mbps. Based on this, we perform thermal analysis and vibration analysis of the system platform. Experimental results show that the system can achieve stable data transmission and storage, and the data is intact and reliable.

Adaptive Buffer Capture and Storage for High-Speed Cameras

The output speed of a high-resolution camera with a fast frame rate is high, reaching 800 MB/s or even more. Consequently, the abundant data recorded can easily cause data overflow during transmission and frame loss during storage. To address this problem of data overflow and frame loss while achieving reliable acquisition rates, herein, we design a high-speed video adaptive transmission and storage method based on the camera link transmission protocol. The system uses the camera link transmission protocol and high-speed cameras for data acquisition. During data transmission, memory space is employed as the data buffer pool, an adaptive memory buffer pool is designed using the hardware and acquisition parameters, and a circular read/write buffer, combined with a block device read/write method, is used inside the buffer pool for data transmission. For data storage, input/output completion port asynchronous storage mixed with frame sequence number filtering is employed to write data, and the adaptive buffer of the hard disk is used to achieve efficient data writing. The experimental results reveal that the proposed method can realize efficient and stable writing of data on conventional industrial cameras based on the camera link interface, effectively addressing the problem of frame loss during data storage. Moreover, the stored data can be transferred efficiently with less resource occupation, thereby meeting the application requirements of high-precision vision measurement systems and demonstrating broad application value.

Badminton Recognition and Tracking System

Human–computer interaction systems have been developed in large numbers and quickly applied to sports. Badminton is the best sport for applying robotics because it requires quick recognition and fast movement. For the development of badminton recognition and tracking systems, it is important to accurately identify badminton, venues, and opponents. In this paper, we designed and developed a badminton recognition and tracking system using two 2 000 000-pixel high-speed cameras. The badminton tracking system has a transmission speed of 250[Formula: see text]fps and the maximum speed of the badminton resonator is 300[Formula: see text]km/h. The system uses the camera link interface Camera Link to capture images of high-speed cameras and process all captured images in real time using different regions of interest settings. In order to improve accuracy, we propose a new method for judging the center point of badminton. We have proposed a detector that detects the four corner points of the field by using the contour information of the badminton court when the approximate position of the badminton court is known. We set the sensing area according to the approximate position of the badminton court and use the histogram in the sensing area to select the point closest to the contour. Specify the intersection of the line as the corner point of the badminton court. The proposed angle detector has a high detection rate. It is more than 10 times more accurate than traditional detectors. The moving badminton is detected by an elliptical detector. We propose a method to find the center of the correct ellipse from the four candidates by selecting the four candidate contours of the ellipse. Compared to conventional circular detectors and points on three-dimensional coordinates, the proposed elliptical detector reduces the error by about 3[Formula: see text]mm.

Focus on lasers, imaging, microscopy, and nanoscience

Focus on lasers, imaging, microscopy, and nanoscience

Framework for High-Performance Video Acquisition and Processing in MTCA.4 Form Factor

The presented framework enables capturing video streams from cameras with a Camera Link interface. It is designed for scalable high-reliability industrial and scientific applications. The solution performs data capture, optionally processing it, and delivers it to a host CPU. It consists of an MTCA.4-compliant frame grabber, its firmware, and a set of software components supporting several different cameras. The framework is focused on Xilinx 7-Series field-programmable gate array (FPGA) circuits. These have I/O pins fast enough to deserialize the Camera Link streams without use of any external components. The reference implementation runs on a hardware platform composed of a dual-slot FMC carrier module equipped with a modern Artix-7 FPGA and up to two Camera Link pass-through modules. The video stream is written to the host computer memory by a custom scatter-gather direct memory access (DMA) engine developed at the Department of Microelectronics and Computer Science (DMCS) of Lodz University of Technology. The framework also includes complete software support consisting of a Linux device driver, application programming interface libraries as well as console and graphical user applications. The proposed video acquisition solution is the world's first Camera Link frame grabber for the MTCA.4 architecture. It enables collecting data from the camera using the top performance 80-bit Camera Link interface, offering 6.8 Gb/s of raw image data throughput. The solution was tested with a number of commercially available cameras.

Increasing of Precision Technology of Glass Sorting Based on Very Fast Reconfigurable Image Processing

The paper deals with a method and technology for increasing of precision sorting of transparent materials - glass. The recycled glass is a valuable material which is necessary as an ingredient in the process of glass manufacturing. We propose a very fast industrial device based on FPGA (field-programmable gate array) image processing along with a novel algorithm for a robust real-time treatment of acquired data. The system consists from a line-scan camera with fast CameraLink interface, FPGA processing, battery of valves propelled via pneumatics and nozzle block. Very important part of the system is a background configuration software enables precise assessment of required limits as inputs to FPGA processing. The overall performance is discussed from the perspective of laboratory and industrial tests. The proposed FPGA image processing can be utilized for further future enhancements in the field of precise sorting of glass with stuck labels on it. The results give very good performance even in the industrial environment with a lot of dust and dirt and hence the glass does not need to be extensively cleaned.

Hardware Design of Multichannel Video Acquisition System Based on FPGA

A hardware design of multi-channel video acquisition system is designed, we propose system based on FPGA Cyclone V chip, The A/D conversion of analog video signal is accomplished through high-speed parallel AD chip LTC2202 of LINEAR Company. In the process of image data acquisition, SDRAM is used for data caching in image processing. From capacity and reading and writing speed analysis, 2 pieces of MICRON Company’s 32 bit wide MT48LC2M32B2B5 are selected, and the capacity is 64Mb, The Cameralink interface is selected as the interface between FPGA and image data transmission of external system. There is reserved communication with external control signals, sending control signals by TI Company DS90LV047. The system collects the image data from the front end through the A/D, caches the SDRAM and outputs the image through Cameralink to achieve the high speed and high efficiency of the data transmission. The hardware realizes the data acquisition and transmission of the multi-channel target image.

Non-Standard Video Protocol Transmission System Design Based on the Camera Link Interface of FPGA

With the rapid development of video communication technology, video transmission is becoming more and more important. However, in the process of video transmission, the reliability and real-time performance of transmission data is the premise of video high-speed transmission, So In order to improve the real-time video image transmission, validity, reliability, and design a Camera Link interface based on FPGA of non-standard video protocol transmission system, the system front-end by simulating the Camera to complete the video image collection, through the video format conversion chip output standard video protocol data, and uses FPGA to complete the processing of video data, complete the video image with Camera Link interface of high speed transmission, finally realizes the real-time video transmission, but also improve the reliability and effectiveness of the video image.

Research on Video Remote Transmission Technology Based on FPGA

In order to solve the problem of remote transmission technology of high speed digital video in the application process, this paper takes FPGA technology as the core, uses the optical fiber communication, Camera link interface technology, and high-speed serial parallel conversion and so on to provide a technical proposal of a high-speed digital video remote transmission. First of all, this paper overall designs the remote transmission technology of digital video, and then designs its hardware circuit and system control logic, focuses on the specific design of digital video acquisition, high-speed data caching and decoding, data sending and receiving and analog camera data. Finally, the debugging and testing of the experimental transmission technology of the remote digital video are carried out, mainly for the single board debugging, analog transmission experiment, and video transmission experiment, in which the debugging results show that the FPGA minimum system meets the requirements. Transmitting and receiving communication circuit and serial communication circuit of Camera link are correct; high-speed serial parallel conversion chip and SFP peripheral circuit are stable and reliable; simulation experiments show that in the process of image transmission, the pixel clock, line effective, field effective; and the sequence of image data is controlled reasonably, which can well achieve image transmission. The video transmission experiment results show that the transmission technology designed can achieve the remote transmission of digital video.

Single software platform used for high speed data transfer implementation in a 65k pixel camera working in single photon counting mode

Integrated circuits designed for specific applications generally use non-standard communication methods. Hybrid pixel detector readout electronics produces a huge amount of data as a result of number of frames per seconds. The data needs to be transmitted to a higher level system without limiting the ASIC's capabilities. Nowadays, the Camera Link interface is still one of the fastest communication methods, allowing transmission speeds up to 800 MB/s. In order to communicate between a higher level system and the ASIC with a dedicated protocol, an FPGA with dedicated code is required. The configuration data is received from the PC and written to the ASIC. At the same time, the same FPGA should be able to transmit the data from the ASIC to the PC at the very high speed. The camera should be an embedded system enabling autonomous operation and self-monitoring. In the presented solution, at least three different hardware platforms are used—FPGA, microprocessor with real-time operating system and the PC with end-user software. We present the use of a single software platform for high speed data transfer from 65k pixel camera to the personal computer.

High-Performance Image Acquisition and Processing System with MTCA.4

Fast evolution of high-performance cameras in recent years has made them promising tools for observing transient and fast events in large-scale scientific experiments. Complex experiments, such as ITER, take advantage of high-performance imaging system consisting of several fast cameras working in the range of visible and infrared light. However, the application of such devices requires a usage of high-performance data acquisition systems able to read and transfer large amount of data, reaching even 10 Gbit/s for a single camera. The MTCA.4 form factor fulfils the requirements of demanding imaging systems. The paper presents a first implementation of a complete image acquisition system built on the basis of MTCA.4 architecture, which is dedicated for the operation with high-resolution fast cameras equipped with Camera Link interface. Image data from the camera are received by the frame grabber card and transmitted to the host via the PCIe interface. The modular structure of MTCA.4 architecture allows connecting several cameras to a single MTCA chassis. The system can operate in two modes: with internal CPU installed in the MTCA chassis or with external CPU connected to the chassis with PCIe link. The usage of the external CPU opens a possibility to aggregate data from different subsystems. The system supports precise synchronization with the time reference using Precise Timing Protocol (IEEE 1588). The timing modules ensure clock distribution and triggers generation on backplane lines. These allow synchronization of image acquisition from different cameras with high precision. The software support for the system includes low-level drivers and API libraries for all components and a high-level EPICS-based environment for system control and monitoring.

Design of Real-Time Large Field Video Display System Based on FPGA

In order to realize the large field or view digital video images into PAL format analog video output,this article introduce a real-time display system of large visual field in the basis of FPGA. Apply the EP2S30F672I4 chip of the StraixII series to be the core processing unit, which is from the Altera; and the CSC12M25BMP19 camera, from the Teli, to be the image data source, with 25 Hz of output frame rate and a resolution of 2048 x 2048 on images. The Cameralink interface is adopted to be the data transmission channel between the camera and interface card, which carries out the configuration of the camera, image data acquisition, caching, image reduction and PAL format conversion, and finally accomplishes the image real-time display.This paper discusses the FPGA implementation of double bilinear interpolation algorithm, including image data frames buffer, the vertical and horizontal interpolation. The experiments results show that our expects are achieved by the algorithm and the hardware implementation.

Test bed for real-time image acquisition and processing systems based on FlexRIO, CameraLink, and EPICS

Image diagnostics are becoming standard ones in nuclear fusion. At present, images are typically analyzed off-line. However, real-time processing is occasionally required (for instance, hot-spot detection or pattern recognition tasks), which will be the objective for the next generation of fusion devices. In this paper, a test bed for image generation, acquisition, and real-time processing is presented. The proposed solution is built using a Camera Link simulator, a Camera Link frame-grabber, a PXIe chassis, and offers software interface with EPICS. The Camera Link simulator (PCIe card PCIe8 DVa C-Link from Engineering Design Team) generates simulated image data (for example, from video-movies stored in fusion databases) using a Camera Link interface to mimic the frame sequences produced with diagnostic cameras. The Camera Link frame-grabber (FlexRIO Solution from National Instruments) includes a field programmable gate array (FPGA) for image acquisition using a Camera Link interface; the FPGA allows for the codification of ad-hoc image processing algorithms using LabVIEW/FPGA software. The frame grabber is integrated in a PXIe chassis with system architecture similar to that of the ITER Fast Controllers, and the frame grabber provides a software interface with EPICS to program all of its functionalities, capture the images, and perform the required image processing. The use of these four elements allows for the implementation of a test bed system that permits the development and validation of real-time image processing techniques in an architecture that is fully compatible with that of the ITER Fast Controllers. This paper provides a specific example of a pattern search in a movie, its real-time implementation, and a performance analysis of the entire platform.

An Optimized Video Capture and Preprocessing Strategy Based on FPGA

The video capture and preprocessing is the basis of video process system. This paper analyzes the timing of video capture by Camera Link interface based on FPGA, and proposed an automatic error detection approach to avoid error accumulation during the video data capture. Furthermore, by adopting the optimized LUT and pipeline addition, an optimized method for RGB to YCbCr color space conversion (CSC) is presented specifically for the video format preprocessing. Experimental results demonstrate that the strategy we proposed is of high reliability, and it could obtain maximum operation frequency of 334MHz, 3.16 times faster than the direct method.

An Optimized Video Capture and Preprocessing Strategy Based on FPGA

The video capture and preprocessing is the basis of video process system. This paper analyzes the timing of video capture by Camera Link interface based on FPGA, and proposed an automatic error detection approach to avoid error accumulation during the video data capture. Furthermore, by adopting the optimized LUT and pipeline addition, an optimized method for RGB to YCbCr color space conversion (CSC) is presented specifically for the video format preprocessing. Experimental results demonstrate that the strategy we proposed is of high reliability, and it could obtain maximum operation frequency of 334MHz, 3.16 times faster than the direct method.

Design of a High Definition Video Communication System in Real-Time Network

This paper presents the design of a high definition video communication system with real-time performance in the network. In order to process and transmit the high definition video, the design combines FPGA and SOC, follows the H.264 video coding compression. The FPGA realizes the highspeed video acquisition via Cameralink interface, and convert the raw image to ITU-R BT.1120 stream. The SOC contains CPU and Codec, it compresses the BT.1120 stream to H.264 steam and transmit the stream in the network. The low-delay rate control algorithm can limit the bitrate in a very low level. The result shows that the system reduces bandwidth and lowers the latency, the design is adaptable to the real time environments.

Implementation of Camera Link Interface on Virtex-5 FPGA

Camera link interface is a standard interface commonly used in current industrial camera and image acquisition card and it is usually realized by special chips. The embedded image processing platform has the FPGA chips, if the camera link interface can be implemented on the FPGA chips, the circuit design will be simplified and the system integration can be improved.

Design and Realization of Embedded High-Speed Image Stabilization Device Base on FPGA+DSP

A design and realization of embedded High-speed image stabilization device is present to remove unwanted shaking phenomena in the image sequences captured by the high-speed industrial camera with 256x256 pixel @1000 frames per second, 8bit, Gray scale. Each module design of the mentioned device is introduced in detail. The interested image sequences are transferred through camera link interface to the device, buffered, preprocessed by an FPGA, and processed by DSP to achieve two-dimensional motion vector which is exported by a digital-to-analog chip. The test result shows that the image stabilization device works stable, real-time, high-accuracy.

Fastcom introduces world's first intelligent CMOS vision system with Camera Link interface

Fastcom introduces world's first intelligent CMOS vision system with Camera Link interface