Calibration Block Research Articles

A real-time digital calibration scheme for the cyclic ADC

A digital calibration scheme to correct the nonlinearity caused by finite amplifier gain and capacitor mismatch for the cyclic analog-to-digital converter (ADC) is presented. The calibration block of correcting the weight of the jumping points is implemented in which adders and registers are utilized without multipliers to reduce the silicon area cost. Each calibration block is shared by five ADCs. Ten switches are added into the 1.5-bit multiplying digital-to-analog converter to choose the test input signal and set the value of the most significant bit for measuring the heights of the jumping points. The capacitor mismatch and gain errors are measured as one error, and then the weight of the jumping points is compensated in the digital domain to improve the linearity of the ADC. Designed in a 0.18μm CMOS technology, the silicon area cost of each ADC is 0.03×1.7mm2 and the power consumption is 0.56mW at a supply voltage of 1.8V. The simulation results show that the calibration improves SNDR to 83.73dB from 55.13dB with 1% capacitance mismatch, and the calibration needs three conversion cycles which makes it real-time to obtain the changing error parameters during normal operation.

An all-digital self-calibrated delay-line based temperature sensor for VLSI thermal sensing and management

This paper presents a low power self-calibrated delay-line based temperature sensor intended for Very Large Scale Integration (VLSI) thermal management applications. It proposes a fully digital automatic self-calibration method that removes the sensitivity to process variations in delay-line based temperature sensors. This method requires only one calibration block to calibrate multiple delay-line based temperature sensors sequentially. Both the proposed temperature sensors and the self-calibration method were verified experimentally on field programmable gate arrays (FPGAs) and on 65nm and 0.13µm custom ICs. The measurement results on three 65nm custom ICs show a resolution of 0.4°C with 3σ errors of ±3.0°C, from 20 to 80°C. The proposed temperature sensors were implemented on a FPGA based VLSI thermal management system. Four microprocessor cores were mapped onto the corners of a Cyclone IV FPGA chip to emulate the VLSI load. Each core has a proposed temperature sensor close by. The runtime thermal profiles were obtained for four microprocessor cores, with eight different Dynamic Thermal Management (DTM) methods. Experimental results from different DTM techniques were studied.

3차원 초음파 시스템의 캘리브레이션 방법

This paper proposes a calibration method for a freehand 3-D ultrasound system in medical robotic research. The calibration block with six wires was designed to set the fixed target points. The positions of the ultrasound probe and calibration block were measured using an optical tracker. The relationship between the position of the ultrasound probe and the pixel coordinates in the images was derived using a calibration process. The scaling matrix was also calculated. The experimental results showed that the proposed method could find solutions using a simple least square method from one or multiple ultrasound images.

PACS photometer calibration block analysis

The absolute stability of the PACS bolometer response over the entire mission lifetime without applying any corrections is about 0.5% (standard deviation) or about 8% peak-to-peak. This fantastic stability allows us to calibrate all scientific measurements by a fixed and time-independent response file, without using any information from the PACS internal calibration sources. However, the analysis of calibration block observations revealed clear correlations of the internal source signals with the evaporator temperature and a signal drift during the first half hour after the cooler recycling. These effects are small, but can be seen in repeated measurements of standard stars. From our analysis we established corrections for both effects which push the stability of the PACS bolometer response to about 0.2% (stdev) or 2% in the blue, 3% in the green and 5% in the red channel (peak-to-peak). After both corrections we still see a correlation of the signals with PACS FPU temperatures, possibly caused by parasitic heat influences via the Kevlar wires which connect the bolometers with the PACS Focal Plane Unit. No aging effect or degradation of the photometric system during the mission lifetime has been found.

Uncertainties of an Automated Optical 3D Geometry Measurement, Modeling, and Analysis Process for Mistuned Integrally Bladed Rotor Reverse Engineering

An automated reverse engineering process is developed that uses a structured light optical measurement system to collect dense point cloud geometry representations. The modeling process is automated through integration of software for point cloud processing, reverse engineering, solid model creation, grid generation, and structural solution. Process uncertainties are quantified on a calibration block and demonstrated on an academic transonic integrally bladed rotor. These uncertainties are propagated through physics-based models to assess impacts on predicted modal and mistuned forced response. Process details are discussed and recommendations made on reducing uncertainty. Reverse engineered parts averaged a deviation of 0.0002 in. (5 μm) which did not significantly impact low and midrange frequency responses. High frequency modes were found to be sensitive to these uncertainties demonstrating the need for future refinement of reverse engineering processes.

1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector

This study presents a 1–5.6 Gb/s CMOS clock and data recovery (CDR) integrated circuit (IC) implemented in a 0.13 μm CMOS process. The CDR uses a half-rate linear phase detector (PD) of which static phase offset is compensated by an additional binary PD and a digital charge pump (CP) calibration block. During initialisation, the static phase offset is detected by the binary PD and the CP current is controlled accordingly to compensate the static phase offset. Also, the architecture of this CDR IC is designed for a clock embedded serial data interface which transfers CDR training clock patterns before normal random data signals. The implemented IC consumes 16–22 mA from a 1.2 V core supply for data rates of 1–5.6 Gb/s and 20 mA from a 3.3 V I/O supply for two preamplifiers and low-voltage differential signalling drivers. When the 231–1 pseudorandom binary sequence is used, the measured bit-error rate is better than 10–12 and the jitter tolerance is 0.3UIpp. The recovered clock jitter is 21.6 and 4.2 psrms for 1 and 5.6 Gb/s data rates, respectively.

Improved corner detection by ultrasonic testing using phase analysis

In ultrasonic testing, corners are used for sensitivity calibration in the form of notches, for measuring the sound velocity in the material, and as known reference points during testing. A 90° corner will always reflect incoming waves in the opposite direction due to a double reflection and therefore give a strong echo. This article presents a method for separating the echo from a corner from other echoes and more accurately find the position of the corner. The method is based on analysing the phase of the reflected signal. The proposed method was tested on a steel calibration block and the width of the indication was reduced by up to 50% compared to the amplitude signal. This results in a more accurate positioning of the corner. Using the phase instead of the amplitude will also improve the reliability, since reflections other than from corners will disappear.

Five-year experience of quality control for a 3D LSO-based whole-body PET scanner: Results and considerations

PET scanners require routine monitoring and quality control (QC) to ensure proper scanner performance. QC helps to ensure that PET equipment performs as specified by the manufacturer and that there have not been significant changes in the system response since acceptance. In this work we describe the maintenance history and we report on the results obtained from the PET system QC testing program over 5 years at two centers, both utilizing a Siemens Biograph 16 HiRez PET/CT system. QC testing programs were based on international standards and included the manufacturer’s daily QC, monthly uniformity and sensitivity, quarterly cross-calibration and annual resolution and image quality.For the Winnipeg and Novara sites, two and one PET detector blocks have been replaced, respectively. Neither system has had other significant PET system related hardware replacements. The manufacturer’s suggested daily QC was sensitive to detecting problems in the function of PET detector elements. The same test was not sensitive for detecting long term drifts in the systems: the Novara system observed a significant deterioration over five years of testing in the sensitivity which exhibited a decrease of 16% as compared to its initial value measured at system installation. The measure of the energy spectrum, showed that the 511keV photopeak had shifted to a position of 468keV. This shift was corrected by having service personnel perform a complete system calibration and detector block setup.We recommend including tests of system energy response and of sensitivity as part of a QC program since they can provide useful information on the actual performance of the scanner. A modification of the daily QC test by the manufacturer is suggested to monitor the long term stability of the system. Image quality and spatial resolution tests have proven to be of limited value for monitoring the system over time.

S-Scan of Ultrasonic Phased Array Testing for Electrofusion Joints of Polyethylene Pipes

Electrofusion joint is used widely for PE pipes; the quality of the joint influences the safety of gas distribution system. Proven and reliable NDT technology of the joint is immature. The attenuation of ultrasound in PE is higher than for metals. Defects Include voids, cracks, bad fusion interfaces, dislocations of heating wires, could find be ultrasonic phased array testing. Examination time, surface of specimen, transducer, calibration block, resolution, examination range and couplant are recommend.

回转体形貌测量中的相机自标定

To realize the automatic calibration of the camera used in morphology measurement of an axisymmetric body,the perspective projection characteristics of the axisymmetric body were investigated,and a automatic calibration method for intrinsic and extrinsic parameters of the measureing camera was proposed based on self constraint characteristics of measured axisymmetric body.Firstly,by utilizing the extration of section fetures easily,the ellipses in the images of axisymmetric body cross sections were estimated to obtain the images of the circular points.Then,combining with the epipolar constraint,the full constraint equations of the image for an absolute conic were established and computed to obtain the camera intrinsic parameters by Cholesky's factorization.Secondly,based on the intrinsic matrix of the camera,the extrinsic parameter equations were established by using the image of the symmetry axis and cross sections to solve the extrinsic parameters.Experimental results indicate that the relative precision of the intrinsic parameters is better than 0.95% and that of the extrinsic parameters is 5.6%.By utilizing only the axisymmetric constraints of the measured object without the calibration plate or block,the calibration process is simple,effective,and can satisfy the real needs.

An undersampling 14-bit cyclic ADC with over 100-dB SFDR

A high linearity, undersampling 14-bit 357 kSps cyclic analog-to-digital convert (ADC) is designed for a radio frequency identification transceiver system. The passive capacitor error-average (PCEA) technique is adopted for high accuracy. An improved PCEA sampling network, capable of eliminating the crosstalk path of two pipelined stages, is employed. Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area. An additional digital calibration block is added to compensate for the error due to defective layout design. The presented ADC is fabricated in a 180 nm CMOS process, occupying 0.65 × 1.6 mm2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range (SFDR), and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.

Measuring the incidence angle of a peizoelectric transducer using a CO-3 calibration block

A technique of using a CO-3 calibration block for measuring not only the base of a piezoelectric transducer (PET) but also its incidence angle is proposed. This approach allows a single specimen to be used in an automated PET certification system for obtaining its main characteristics. The results of measuring the PET incidence angle in an automated mode on a CO-3 block are compared with the measurement results on CO-2 according to GOST (State Standard) 14782–86. It is shown that systematic error is absent. The use of a CO-3 block substantially reduces the time of obtaining the basic characteristics of a PET and simplifies the calibration procedure.

Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting

Design of a fast-locking phase-locked loop (PLL) is one of the major challenges in today's wireless communications. A recently reported digitally controlled oscillator (DCO)-based all-digital PLL (ADPLL) can achieve an ultrashort settling time of 10 µs. This study describes a new DCO tuning word (OTW) presetting technique for the ADPLL to further reduce its settling time. Estimating the required OTW is the most crucial issue for presetting. Two methods are proposed here to estimate the required OTW. One method is using a foreground calibration block to eliminate the effect of DCO gain (KDCO) estimation error (ɛK) and then directly calculating the required OTW for the process/voltage/temperature calibration (PVT-calibration) mode of the ADPLL. The other method is using a new counter-based mode switching controller (CB-MSC) to estimate the required OTW for the acquisition mode and tracking mode. This method is based on the ADPLL's inherent characteristic of frequency toggling and is independent of loop parameters. Furthermore, our proposed presetting technique can be used with the dynamic loop bandwidth control technique together. The ADPLL with the proposed OTW estimating and presetting block is designed using very-high-speed integrated circuit hardware description language and simulated in ModelSim environment. Simulation results demonstrate that a minimum settling time of 2.9 µs is achieved and the improvement is about 40–50% on average compared with the ADPLL without our techniques.

Single-VCO multi-band DTV frequency synthesizer with a divide-by-3 frequency divider for quadrature signal generation

A multi-band frequency synthesizer for In-phase and Quadrature (I/Q) LO signal generation in Digital TV tuners is presented. Using divisor numbers other than powers of 2 (2 n ) for quadrature generation, reduces the required frequency range of the VCO, hence the number of VCO circuits, in multi-band frequency synthesizers. In the proposed synthesizer, VHF, UHF and L-band frequencies are covered with only one VCO. This is achieved by using a novel divide-by-3 circuit which produces precise I/Q LO signals. The VCO tuning range in this design is 2,400---3,632 MHz which is covered by a 6-bit switched-capacitor bank. A fast adaptive frequency calibration block selects the closest VCO frequency to the target frequency by setting the coarse-tuning code prior to the start of phase lock. A programmable charge pump is used to reduce variations in PLL characteristics over the frequency range. The synthesizer has been fabricated in a 0.18 μm CMOS technology and the die area is 1.7 � 1.6 mm2. It consumes 27 mA from a 1.8 V power supply. Measurement results show operation of the proposed divide-by-3 circuit over the entire VCO frequency range. The synthesizer quadrature output phase noise for UHF and VHF bands is <�131dBc/Hz at 1.45 MHz offset.

Calibration of particle position on digital holography using transparent resin block with dispersed particles

This paper describes the use of a Calibration Block (CB) for evaluating the accuracy of digital holography in particle position measurement. CB made of acrylic has three layers and the gap between the layers is filled with transparent resin. The refractive index of the resin and the layers is almost the same (1.49). Fin Block (FB), which is not filled with resin, is introduced in order to evaluate effects of the resin. The fringe edges of several holographic patterns are observed by using three kinds of CB and FB. Each layer is coated with spherical particles (diameter: 16.36 ± 0.42 μ m). The influence of multiple scattering on the detected depth of the particles is evaluated by changing the number density of particles. Three kinds of CB and FB are prepared (averaged particle density in the holographic pattern; 83.2, 166.5 and 249.7). The fringe edges of the holographic patterns generated in CB and FB are observed, respectively. It is found that the fringe edges of CB are clearer than FB. Also, Multiple scattering acts as a source of background noise with high spatial frequency, which has almost the same frequency as that of the particle diffraction on the fringe patterns, and reduces the effective signal-to-noise ratio of the holographic pattern. CB can be used to evaluate the influence of multiple scattering on the detected particle depth.

Self-Reported Physical Activity Improves Prediction of Body Fatness in Young Adults

To examine self-reported physical activity levels from the International Physical Activity Questionnaire (IPAQ) as an independent predictor of dual-energy x-ray absorptiometry (DXA)-measured percent body fat (%BF) from body mass index (BMI), gender, and race. Two hundred and seventy-eight students, aged 18-24 yr, volunteered to participate. There were 133 males (85 white and 48 black) and 145 females (77 white and 68 black). Total activity levels were quantified in MET hours per week (MET h wk(-1)) using the IPAQ short form. Height and weight were measured, and BMI values were calculated (kg m(-2)). %BF was assessed using DXA. Linear regression analysis was used to develop and compare a body fat prediction equation with (full) and without (reduced) the variable MET-h.wk. Both models included BMI, gender, and race as predictor variables. The prediction sum of squares (PRESS) statistic was used to cross-validate both models, and the individual predictive accuracy was compared using modified Bland-Altman plots. Mean +/- SD values were as follows: BMI = 24.4 +/- 4.1 kg m(-2), %BF = 24.5 +/- 9.3%, and MET h wk(-1) = 37.4 +/- 21.9. Gender, BMI, and race explained 81% of the variance in %BF, with a root mean square error (RMSE) of 4.07. The full model with MET-h.wk improved the prediction of %BF by 2% (R2 = 0.83, RMSE = 3.87). When cross-validated, the corresponding PRESS statistics for the reduced and full model were 4.10 and 3.90, respectively. Bland-Altman limits of agreement were greater for the reduced model compared with the full model (-8.09, 8.10 vs -7.67, 7.68). These results suggest that %BF can be predicted with greater precision and accuracy in a young adult population when MET-h.wk are included in addition to BMI, gender, and race.

A High IIP2 Direct-Conversion Receiver Using Even-Harmonic Reduction Technique for Cellular CDMA/PCS/GPS Applications

A high IIP2 direct-conversion receiver for cellular CDMA/PCS/GPS has been developed in a 0.35 mum SiGe BiCMOS process. This receiver consists of a RF front-end chip and a base-band chip. The RF front-end chip includes three LNAs, three mixer cores with a common output stage, and LO distribution blocks. The base-band chip includes a channel selection filter, an output buffer, and a DC calibration block. To achieve high IIP2 performance, an even-harmonic reduction technique is proposed based on a simplified analysis of second-order intermodulation. A 40-dB improvement of the IIP2 performance is accomplished by this technique, which reduces sensitivity to operating conditions and to output load mismatches. This receiver also attains high IIP3 and a low-noise figure. Measurement results show 71 dBm IIP2, -1.3 dBm IIP3, and 2.4 dB NF for Cellular CDMA; 68 dBm IIP2, - 3.7 dBm IIP3, and 2.9 dB NF for PCS; and 26 dBm IIP2 -30 dBm IIP3, and 2 dB NF for GPS.

A novel depth-from-focus-based measurement system for the reconstruction of surface morphology with depth discontinuity

Errors due to magnification variations are caused in optical systems when three-dimensional shape measurements based on depth-from-focus (DFF) are performed. These magnification variations cause focus measures to be incorrectly interpreted. In this paper, a DFF-based system which considers the magnification variations has been developed to undertake accurate measurements of surface morphology with depth discontinuity. The image magnification can be represented by magnification factors, which are computed using the ratio of diagonal image lengths of a rectangular calibration block, according to optical system movements. The image calibration is performed using the magnification factors. The calibration makes the image size of the object features identical, in spite of magnification variations resulting from optical system movements. Therefore, the application of accurate and reliable focus measures is made in the calibrated images. The performance of our presented system has been verified through experiments with actual objects with depth discontinuity.

Ultrasonic imaging using a computed point spread function

An explicit point spread function (PSF) evaluator in the frequency domain is described for an ultrasonic transducer operating in the pulse-echo mode. The PSF evaluator employs the patch element model for transducer field determination and scattered field assessment from a small but finite "point" reflector. The PSF for a planar transducer in a medium has been evaluated in the near and the far field. The computed PSFs were used to deconvolve and restore surface images, obtained experimentally, of a single hole and a five-hole cluster in an Al calibration block. A calibration plot is arrived at for estimating, without the need for deconvolution, the actual diameters of circular reflectors from apparent diameters obtained experimentally for a single-medium imaging configuration. The PSF, when the transducer and the point reflector are in two media separated by a planar interface, was evaluated in the near and far field. The computed PSFs were used to deconvolve and restore subsurface images, obtained experimentally, of flat bottom holes (FBHs) in an Al calibration block. We show that the PSF, in the presence of a planar interface, can be obtained from a single-medium PSF model using an effective single-medium path length concept. The PSFs and modulation transfer functions (MTFs) are evaluated for spherical focused and annular transducers and compared with those for the planar transducer. We identify imaging distances to get better-resolved images when using planar, spherical focused, and annular transducers.

Development and certification of the MAΓEOC calibration block for magnetic properties of a pipeline with local heterogeneities

Some general features of metrological supplementation for techniques and means of nondestructive testing of materials and articles are discussed. In particular, the CO MAГEOC calibration block for magnetic properties of a pipeline with local inhomogeneities that was developed and certified at CПEKTP, in cooperation with the Ural Research Institute of Metrology (ФГУП УНИИМ), is considered.