Cache Memory Research Articles

Deep Learning-Based Content Caching in the Fog Access Points

Proactive caching of the most popular contents in the cache memory of fog-access points (F-APs) is regarded as a promising solution for the 5G and beyond cellular communication to address latency-related issues caused by the unprecedented demand of multimedia data traffic. However, it is still challenging to correctly predict the user’s content and store it in the cache memory of the F-APs efficiently as the user preference is dynamic. In this article, to solve this issue to some extent, the deep learning-based content caching (DLCC) method is proposed due to recent advances in deep learning. In DLCC, a 2D CNN-based method is exploited to formulate the caching model. The simulation results in terms of deep learning (DL) accuracy, mean square error (MSE), the cache hit ratio, and the overall system delay is displayed to show that the proposed method outperforms the performance of known DL-based caching strategies, as well as transfer learning-based cooperative caching (LECC) strategy, randomized replacement (RR), and the Zipf’s probability distribution.

Acceleration of vector bilateral filtering for hyperspectral imaging with GPU

SummaryFor hyperspectral imaging, the vector bilateral filter usually leads to better performance when compared with the traditional 2D bilateral filter. However, the large computation complexity of vector bilateral filtering makes it an extremely time cost algorithm. To overcome this challenge, a GPU‐based acceleration for vector bilateral filtering called vBF_GPU was proposed in this paper. To improve the efficiency of the cache memory usage, multiple CUDA threads were utilized to processing one pixel of the hyperspectral image in vBF_GPU. The memory access operation of vBF_GPU was fully optimized to reduce the memory access cost of the GPU program. The experiment results indicated that vBF_GPU can provide more than 30× speedup when compared with an octa‐core CPU implementation and more than 20× speedup when compared with a naïve GPU implementation of vector bilateral filtering.

Strategy and algorithms for the parallel solution of the nearest neighborhood problem in shared-memory processors

The neighborhood problem appears in many applications of computational geometry, computational mechanics, etc. In all these situations, the main requirement for a competitive implementation is performance, which can only be attained in modern hardware by exploiting parallelism. However, whereas the performance of serial algorithms is fairly predictable, that of parallel methods depends on delicate issues that have a huge impact (cache memory, cache misses, memory alignment, etc.), but are not easy to control. Even if there is not a simple approach to deal with these factors in shared-memory architectures, it is quite convenient to program parallel algorithms where the data are segregated on a per-thread basis. With this objective in mind, we propose a strategy to develop parallel algorithms based on a two-level design, and apply it to efficiently solve the nearest neighborhood problem. At a higher level, the proposed methods orchestrate the parallel algorithm and split the space into cells stored in a hash table; at the lower level, our methods hold serial search algorithms that are completely agnostic to the high-level counterpart. Using this strategy, we have developed a library combining different serial and parallel algorithms, optimized them, and assessed their performance. The analysis carried out allows to better understand the main bottlenecks in the algorithmic solution of the nearest neighborhood problem and come out with very fast implementations that improve existing available software.

MESI protocol for multicore processors based on FPGA

In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultaneously for more than one task or all the cores working in parallel for the same task. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So, if one core requests a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores. This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using VHDL coding and implemented using ISE Xilinx software, one protocol was used in this design, the MESI (Modify, Exclusive, Shared and Invalid) protocol. Test results were taken by using test bench, and showed all the states of the protocols are working correctly.

MESI protocol for multicore processors based on FPGA

In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultaneously for more than one task or all the cores working in parallel for the same task. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So, if one core requests a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores. This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using VHDL coding and implemented using ISE Xilinx software, one protocol was used in this design, the MESI (Modify, Exclusive, Shared and Invalid) protocol. Test results were taken by using test bench, and showed all the states of the protocols are working correctly.

Coded Caching in the Presence of a Wire and a Cache Tapping Adversary of Type II

This paper introduces the notion of cache-tapping into the information theoretic models of coded caching. The wiretap channel II in the presence of multiple receivers equipped with fixed-size cache memories, and an adversary which selects symbols to tap into from cache placement and/or delivery is introduced. The legitimate terminals know neither whether placement, delivery, or both are tapped, nor the positions in which they are tapped. Only the size of the overall tapped set is known. For two receivers and two files, the strong secrecy capacity- the maximum achievable file rate while keeping the overall library strongly secure- is identified. Lower and upper bounds on the strong secrecy file rate are derived when the library has more than two files. Achievability relies on a code design which combines wiretap coding, security embedding codes, one-time pad keys, and coded caching. A genie-aided upper bound, in which the transmitter is provided with user demands before placement, establishes the converse for the two-files case. For more than two files, the upper bound is constructed by three successive channel transformations. Our results establish provable security guarantees against a powerful adversary which optimizes its tapping over both phases of communication in a cache-aided system.

Countermeasures of interest flooding attack in named data networking: A survey

Named data networking (NDN) is a typical representation and implementation of information-centric networking and serves as a basis for the next-generation Internet. However, any network architectures will face information security threats. An attack named interest flooding attack (IFA), which is evolved, has becomes a great threat for NDN in recent years. Attackers through insert numerous forged interest packets into an NDN network, making the cache memory of NDN router(s) overrun, interest packets for the intended users. To take a comprehensive understanding of recent IFA detection and mitigation approaches, in this paper, we compared nine typical approaches to resolving IFA attacks for NDN, which are interest traceback, token bucket with per interface fairness, satisfaction-based interest acceptance, satisfaction-based push back, disabling PIT exhaustion, interest flow control method based on user reputation and content name prefixes, interest flow balancing method focused on the number of requests on named data networking, cryptographic route token, Poseidon local, and Poseidon distributed techniques. In addition, we conducted a simulation using Poseidon, a commonly used IFA resolution approach. The results showed that Poseidon could resolve IFA issues effectively.

Hardware Trojan Attack in Embedded Memory

Static Random Access Memory (SRAM) is a core technology for building computing hardware, including cache memory, register files and field programmable gate array devices. Hence, SRAM reliability is essential to guarantee dependable computing. While significant research has been conducted to develop automated test algorithms for detecting manufacture-induced SRAM faults, they cannot ensure detection of faults deliberately implemented in the SRAM array by untrusted parties in the integrated circuit development flow. Indeed, such hardware Trojan attacks represent an emerging security threat. While a growing body of research addresses Trojan designs in logic circuits, little research has explored hardware Trojan attacks in embedded memory arrays [20]. In this article, we propose a new class of hardware Trojans targeting embedded SRAM arrays. The Trojans are designed to evade industry standard post-manufacturing tests while enabling attacks targeting various system hardware components during deployment. Transistor-level simulation results demonstrate minimal impact on SRAM power, performance, and stability while Trojans are not activated. We also prove the feasibility of Trojan insertion in foundries by showing the proposed layouts that preserve the SRAM cell footprint and incur zero silicon area overhead. Finally, we elaborate on several system-level attacks that can leverage these Trojans to compromise security and privacy.

Improving security against cache memory attacks for dual field multiplier design based on elliptic curve cryptography

The elliptic curve cryptographic (ECC) technique is employed for various security standards like security key management, digital signature and data authentication. The ECC technique is capable of undertaking sequential and equivalent mode processes through the unified design that is used equally for binary field and in the leading area of cryptosystems. Furthermore, a progressive transposition method and control information route are combined with the ECC mainframe, which offers efficient throughput, and adaptive calculation with low power. The dual-field Montgomery multiplier-carry save adder (DMM-CSA) structure is designed for the ECC system. The DMM structure has been developed using CSA in this method. The adder requires more number of Full Adders for the circuit design, which has occupied more area. To overcome this problem, this work introduces the dual field Vedic multiplier-look up table carry select adder (DVM-LCSLA) which is used to increase the performance of the ECC scheme for 256 bit. The first aim of the methods mentioned above is to develop a high-performance modular inversion for the ECC technique by employing application specified integrated chip and field programmable gate array (FPGA) implementation with the help of Verilog code. FPGA results indicate the analysis of power utilization, time delay information and Hardware area overhead in DVM-LCSLA used in ECC system compared to the state-of-art methods.

Improved memory management for solving neutron transport via a novel Modular Ray Tracing (MRT) approach embedded in parallel method of characteristic (MOC) framework

Poor memory management can be considered as the first restrictive barrier to the implementation of the neutron transport equation for large reactors. The current research presents a new MRT with the ability to reduce the required memory and increase cache coherency. Also, given the high impact of the angular quadrature set used in the transport calculation, the effects of the angular set are investigated. As a reliable trial for an angular quadrature set examination, comparisons between the Forward and Adjoint transport calculations are performed.Three types of angular quadrature sets are adopted for our optimized MOC steady-state calculation. Based on two known constraints for the quadrature set evaluation, the accuracy and computational cost of the presented sets are examined. Satisfying these two conditions, our implemented Legendre-Chebyshev quadrature set with S20 angular order results in 7.0000E-06 and the 9.0000E-06 difference with reference Keff of G5G7 benchmark in the forward and adjoint calculation respectively. As well, our optimized parallel algorithm for MOC results in 6.18 speedup with 16 threads.

On the Fundamental Limits of Fog-RAN Cache-Aided Networks With Downlink and Sidelink Communications

Maddah-Ali and Niesen (MAN) in 2014 showed that coded caching in single bottleneck-link broadcast networks allows serving an arbitrarily large number of cache-equipped users with a total link load (bits per unit time) that does not scale with the number of users. Since then, the general topic of coded caching has generated enormous interest both from the information theoretic and (network) coding theoretic viewpoint, and from the viewpoint of applications. Building on the MAN work, this paper considers a particular network topology referred to as cache-aided Fog Radio Access Network (Fog-RAN), that includes a Macro-cell Base Station (MBS) co-located with the content server, several cache-equipped Small-cell Base Stations (SBSs), and many users without caches. Some users are served directly by the MBS broadcast downlink, while other users are served by the SBSs. The SBSs can also exchange data via rounds of direct communication via a side channel, referred to as “sidelink”. For this novel Fog-RAN model, the fundamental tradeoff among (a) the amount of cache memory at the SBSs, (b) the load on the downlink (from MBS to directly served users and SBSs), and (c) the aggregate load on the sidelink is studied, under the standard worst-case demand scenario. We propose a converse bound whose key novelty is to jointly bound the downlink load an the sidelink load. For the achievability, by leveraging the network topology, we propose two classes of memory-loads point, where the SBS sidelink load is minimum and the MBS downlink load is minimum, respectively. By memory-sharing between these two classes of memory-loads points, some exact or order optimality results are obtained. Several existing models (e.g., Device-to-Device coded caching, single bottleneck-link coded caching with shared caches, single bottleneck-link caching coded caching with cache-less users) are recovered as special cases of this network model and by-product results of independent interest are given. Finally, the role of topology-aware versus topology-agnostic caching is discussed.

Energy-Efficient Shared Cache Using Way Prediction Based on Way Access Dominance Detection

To meet the performance demands of chip multi-processors, chip designers have increased the capacity and hierarchy of cache memories. Accordingly, a shared lower-level cache reduces conflict misses by adopting a multi-way set-associative structure with high associativity. This structure allows fast access because it allows access to all the ways in the cache set in parallel. However, it consumes a large amount of dynamic energy. Therefore, various schemes have been proposed to increase the cache memory energy efficiency. These schemes use way prediction or partial comparison to reduce unnecessary way accesses. This paper proposes a way prediction algorithm suitable to a shared second-level cache with high associativity. This algorithm is based on the real-time way access dominance detection (WADD). Through this detection, the proposed algorithm can determine the number and location of way candidates suitable for each partial access pattern among the fragmented access patterns due to the first-level cache replacement policy and intermingled accesses by multiple cores. Through this process, the proposed algorithm can implement efficient way prediction. Simulation results show that the WADD exhibits the highest energy efficiency among the comparison group, thus reducing the energy-delay product by 13.5% compared with the conventional cache without way prediction. This result is achieved by reducing the way prediction penalty through fast detection and high prediction accuracy.

Streamlining Active Set Method in MPC using Cache Memory

Abstract This paper investigates how various caching strategies can reduce the computational effort of the active set method (ASM) applied to solve constrained model predictive control problems with quadratic objective function and linear constraints. Specifically, we show that during closed-loop operation, the active set method often re-visits the same combination of active constraints while searching for optimal control inputs by factoring Karush-Kuhn-Tucker (KKT) systems. By storing the factors of the corresponding KKT system in a cache, these repetitive calculations can be simplified to a mere cache search and evaluation of the appropriate factors. Since the cache memory is typically fairly restricted, the efficiency of the scheme depends on how well the cache space can be utilized. In particular, when the cache is fully utilized, and a new element needs to be stored, the cache replacement policy needs to determine which element should be removed from the cache to make space for the new one. In the paper, we scrutinize various cache replacement policies and how well they work as a function of the cache size. The results show that by using a cache of modest size, the number of computational operations performed by the ASM can be reduced by up to 80%, thus significantly accelerating the implementation of model predictive control.

Characterizing Performance of Graph Neighborhood Communication Patterns

Distributed-memory graph algorithms are fundamental enablers in scientific computing and analytics workflows. A majority of graph algorithms rely on the graph neighborhood communication pattern, i.e., repeated asynchronous communication between a vertex and its neighbors in the graph. The pattern is adversarial for communication software and hardware due to high message injection rates and input-dependent, many-to-one traffic with variable destinations and volumes. We present benchmarks and performance analysis of graph neighborhood communication on modern large-scale network interconnects from four supercomputers: ALCF Theta, NERSC Cori, OLCF Summit and R-CCS Fugaku. Our benchmarks characterize communication from the perspectives of latency and throughput. Benchmark parameters make it possible to mimic the behaviors of complex applications on real world or synthetic graphs by varying work distribution, remote edges, message volume, and per-vertex work. We find that minor changes in the input graph can substantially increase latencies; and contention can develop in memory caches and network stacks before contention in the network itself. Further, latencies and contention vary significantly for different graph neighborhoods, motivating the need for exploring asynchronous algorithms in greater detail. When adding work, load imbalance on real-world graphs can be pronounced: latencies for the 99th percentile were 8–128× than the corresponding average latencies. Our results help analysts and developers understand the performance implications of this important pattern, especially for the impending exascale platforms.

Algorithms and Data Structures for New Models of Computation

In the early days of computer science, the community settled on a simple standard model of computing and a basic canon of general purpose algorithms and data structures suited to that model. With isochronous computing, heterogeneous multiprocessors, flash memory, energy-aware computing, cache and other anisotropic memory, distributed computing, streaming environments, functional languages, graphics coprocessors, etc., the basic canon of algorithms and data structures is not enough. Software developers know of real-world constraints and new models of computation and use them to design effective algorithms and data structures. These constraints motivate the development of elegant algorithms with broad utility. As examples, we present four algorithms that were motivated by specific hardware nuances, but are generally useful: reservoir sampling, majority of a stream, B-heap, and compacting an array in $\Theta (\log n)$Θ(logn) time.

Runtime Randomized Relocation of Crypto Libraries for Mitigating Cache Attacks

Crypto libraries such as OpenSSL and Libgcrypt are essential building blocks for implementing secure cloud services. Unfortunately, these libraries are subject to cache side-channel attacks, which are more devastating in cloud environments where inevitable cache contention among different tenants occurs. Previous approaches for mitigating cache side-channel attacks have limitations in terms of the deployability and security; these hinder utilization in cloud services. In this paper, we propose an R2-relocator, a novel library protection technique based on moving target defence. When injected into a running process, the R2-relocator performs randomized relocation of the library during runtime. By doing this, it transforms a vulnerable crypto library into one that randomly changes its memory (cache) location, thereby preventing the delivery of cache side-channel attacks against the library. The proposed technique achieves robust protection against cache side-channel attacks for all crypto libraries, even those containing unpatched critical vulnerabilities, without the need for reconfiguration of the library. Extensive evaluations of security, performance, and deployability of the R2-relocator demonstrate its effectiveness for secure cloud services.

Low Power Single Bit Cache Memory Architecture

A quantitative and yield analysis of single bit cache memory architecture has been analyzed. A single bit cache memory architecture is made up of a write driver circuit, static random access memory cell, and sense amplifiers such as voltage mode sense amplifier and a current-mode sense amplifier. Apart from it, the power reduction technique has been applied over different blocks of single bit cache memory architecture such as sense amplifiers and static random access memory cell, to optimize the power consumption of the circuit. To check the robustness of the circuit monte carlo simulation and process corner simulation also have been done. The conclusion arises that single bit cache memory architecture having volatge mode sense amplifier with forced stack technique over static random access memory in an architecture consumes the lowest power (9.108 µW) with an area of 6.613 × 30.48 mm2.

Security aspects related cache memories in the system files

Security aspects related cache memories in the system files

Field-Free Spin-Orbit Torque Switching in Magnetic Tunnel Junction Structures With Stray Fields

Spin-orbit torque (SOT) offers ultrafast magnetic switching in the subnanosecond regime for magnetoresistive random-access memory (MRAM) as an alternative to future cache memories. However, one main obstacle to the development of perpendicular SOT-MRAM is that a small in-plane external field is required to achieve deterministic magnetization switching. Here we eliminate the external magnetic field for deterministic SOT switching by utilizing the stray field in a magnetic tunnel junction (MTJ) structure. The MTJ consists of a perpendicularly magnetized CoFeB free layer and an in-plane magnetized reference layer that provides a stray field. Unlike usual SOT switching in a single ferromagnet, four switching phases as well as unique critical switching current dependence on the applied in-plane magnetic fields have been observed. This letter demonstrates the effectiveness of stray-field assisted field-free SOT switching in MTJ structures that may extend to eliminate the main obstacle of SOT-MRAM in practical applications.

3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison

Recent development in memory technologies has introduced Spin-Transfer Torque Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip cache memories. Besides its lower leakage power, higher density, immunity to radiation-induced particles, and non-volatility, an unintentional bit flip during read operation, referred to as read disturbance error, is a severe reliability challenge in STT-MRAM caches. One major source of read disturbance error in STT-MRAM caches is simultaneous accesses to all tags for parallel comparison operation in a cache set, which has not been addressed in previous work. This paper first demonstrates that high read accesses to tag arrays extremely increase the read disturbance rate and then proposes a low-cost scheme, so-called Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison (3RSeT), to reduce the error rate by eliminating a significant portion of tag reads. 3RSeT proactively disables the tags that have no chance for hit, using low significant bits of the tags on each access request. Our evaluations using gem5 full-system cycle-accurate simulator show that 3RSeT reduces the read disturbance rate in the tag array by 71.8%, which results in 3.6x improvement in Mean Time To Failure. In addition, the energy consumption is reduced by 62.1% without compromising performance and with less than 0.4% area overhead.