Cache Memory Research Articles

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

This paper provides an overview of blockchain technology’s security and privacy features, as well as an overview of IoT-based cache memory and single-bit six transistor static random-access memory cell sense amplifier architecture. Each chip’s memory is used for recorded as blocks, which are encrypted and used as a blockchain for other memory devices. The architectures comprise of the circuit of write driver, six transistor static random access memory cells, and sense amplifiers such as current differential sense amplifier, charge transfer differential sense amplifier, and voltage latch sense amplifier. Furthermore, different parameters such as the number of transistors, sensing delay, and power consumption have been analyzed for varying resistance values (i.e., R= <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42.3\Omega $ </tex-math></inline-formula> and R=42.3K <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega$ </tex-math></inline-formula> ). Apart from that, power reduction techniques such as dual sleep, forced stack, sleep transistor, and sleep stack are used to optimize power consumption. These power reduction techniques are applied over different blocks of architecture, such as six transistors static random access memory cell and sense amplifier to optimize power consumption of the architecture. The conclusion arises that a single-bit six transistor static random access memory cell with power reduction dual sleep technique voltage latch sense amplifier with power reduction dual sleep technique in architecture consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.65~\mu \text{W}$ </tex-math></inline-formula> of power and has 33 transistors which are lowest from other architectures.

PROWL: A Cache Replacement Policy for Consistency Aware Renewable Powered Devices

Energy harvesting systems powered by renewable energy sources employ hybrid volatile-nonvolatile memory to enhance energy efficiency and forward progress. These systems have unreliable power sources and energy buffers with limited capacity, so they complete long-running applications across multiple power outages. However, a power outage might cause data inconsistency, because the data in nonvolatile memories are persistent, while the data in volatile memories are unsteady. State of the art studies proposed various memory architectures and compiler-based techniques to tackle the data inconsistency in these systems. These approaches impose too many unnecessary check-points on the system to avoid data inconsistency. These studies did not consider the effect of cache memory to mask and postpone the imposed check-points on the system for the sake of consistency. In this article, we utilize the cache memory and propose PROWL, a consistency aware cache replacement policy to avoid data inconsistency with fewer check-points. The results show that PROWL has by up to 85 percent fewer check-points compare to the state of the art approaches, and PROWL improves the average response time of the system by up to 65 percent.

Cache Memory Design for Single Bit Architecture with Different Sense燗mplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster, but this is not always the case. Most of the time, these caches are made of static random access memory cells. They take up a lot of space on the chip and use a lot of electricity. A lot of the time, low power is more important than several aspects. This is true for phones and tablets. Cache memory design for single bit architecture consists of six transistors static random access memory cell, a circuit of write driver, and sense amplifiers (such as voltage differential sense amplifier, current differential sense amplifier, charge transfer differential sense amplifier, voltage latch sense amplifier, and current latch sense amplifier, all of which are compared on different resistance values in terms of a number of transistors, delay in sensing and consumption of power. The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34 μW of power which shows that power is reduced up to 83%, 77.75% reduction in the case of the current differential sense amplifier, 39.62% in case of charge transfer differential sense amplifier and 50% in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture. Furthermore, power reduction techniques are applied over different blocks of cache memory architecture to optimize energy. The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078 μW of power, i.e., reduce 28% more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020. It also presents proposals that use interference reduction techniques without considering the predictability issue. The survey highlights interference sources and categorizes proposals from the perspective of the shared resource. It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis. Every section contains an overview of each proposal and an assessment of its advantages and disadvantages.

Towards Dependency-Aware Cache Management for Data Analytics Applications

Memory caches are being used aggressively in today's data analytics systems such as Spark, Tez, and Piccolo. The significant performance impact of caches and their limited sizes call for efficient cache management in data analytics clusters. However, prevalent data analytics systems employ rather simple cache management policies-notably Least Recently Used (LRU) and Least Frequently Used (LFU)-that are oblivious to the application semantics of data dependency, expressed as directed acyclic graphs (DAGs). Without this knowledge, cache management can, at best, be performed by guessing the future data access patterns based on history, which frequently results in inefficient, erroneous caching with a low hit rate and a long response time. Worse still, the lack of data dependency knowledge makes it impossible to retain the all-or-nothing cache property of cluster applications, in that a compute task cannot be sped up unless all the dependent data has been kept in the main memory. In this paper, we propose a novel cache replacement policy, named Least Reference Count (LRC), which exploits the application's data dependency information to optimize the cache management. LRC keeps track of the reference count of each data block, defined as the number of dependent child blocks that have not been computed yet, and always evicts the block with the smallest reference count. Furthermore, we incorporate the all-or-nothing requirement into LRC by coordinately managing the reference counts of all the input data blocks for the same computation. We demonstrate the efficacy of LRC through both empirical analysis and cluster deployments against popular benchmarking workloads. Our Spark implementation shows that, the proposed policies well address the all-or-nothing requirement and significantly improve the cache performance. Compared with LRU and a recently proposed caching policy called MEMTUNE, LRC improves the caching performance of typical workloads in production clusters by 22% and 284%, respectively.

Population size influence on the energy consumption of genetic programming

Evolutionary Algorithms (EAs) are routinely applied to solve a large set of optimization problems. Traditionally, their performance in solving those problems is analyzed using the fitness quality and computing time, and the effect of evolutionary operators on both metrics is routinely used to compare different versions of EAs. Nevertheless, scientists face nowadays the challenge of considering the energy efficiency in addition to computational time, which requires studying the energy consumption of algorithms. This paper discusses the interest of introducing power consumption as a new metric to analyze the performance of standard genetic programming (GP). Two well-studied benchmark problems are addressed on three different computing platforms, and two different approaches to measure the power consumption have been tested. Analyzing the population size, the results demonstrates its influence on the energy consumed: a non-linear relationship was found between size and energy required to complete an experiment. This analysis was extended to the cache memory and results show an exponential growth in the number of cache misses as the population size increases, which affects the energy consumed. This study shows that not only computing time or solution quality must be analyzed, but also the energy required to find a solution. Summarizing, this paper shows that when GP is applied, specific considerations on how to select parameter values must be taken into account if the goal is to obtain solutions while searching for energy efficiency. Although the study has been performed using GP, we foresee that it could be similarly extended to EAs.

Neuromorphic In-Memory RRAM NAND/NOR Circuit Performance Analysis in a CNN Training Framework on the Edge for Low Power IoT

Training a CNN involves computationally intense optimization algorithms to fit the network using a training dataset, to update the network weight for inferencing and then pattern classification. Hence, the application of in-memory computation would enable a highly power-efficient low latency on-the-edge CNN training technique by avoiding the memory wall created during the external memory read/write operation (for off chip instruction and data transfer). A memory write-verify, and re-program technique can control the RRAM variability. Still, memory verification and re-program is a complex process with additional resources needed for practical implementation of verification circuit. In this study, we have demonstrated a practical (First-in Max-Out) FIMO-based cache memory called Maximum Count Binary Comparator Layer (MCBC), using 1T3R, 1T5R, and 1T7R RRAM structures by using a probability-based accuracy improvement architecture, without the conventional verification process. We constructed 10 layered modified MobileNET with filter size ranging from 32 - 512 and trained with Traffic Sign Recognition Database (TSRD) using a three-tier abstraction simulation learning framework - (1) High level, 10 layered CNN implementation with Python+TensorFlow; (2) Verilog HDL based FP32MUL and FP32ADD (32-bits Floating Point adder and multiplier) circuits constructed with RRAM NAND gates using 1T2R structures; and (3) Digital Look-Up-Table (LUT) model for RRAM variability. An edge learning framework (for the forward pass) is demonstrated using digital RRAM-NAND/NOR universal gates integrated with the Maximum Count Binary Comparator Layer (MCBC) to partially circumvent the impact of RRAM variability and to quantify the RRAM variability on the CNN training prediction accuracy for 65nm CMOS OxRAM (TiN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Hf/TiN) with varying device current compliance of 5, 10, and 50μA for low power IoT applications. The MCBC layer was simulated using a SPICE model, for which the estimated chip layout is 1150 × 1230 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per logical gate input, which resulted in an overall prediction accuracy improvement from 10% to 60% by repeating the logical operations of the NOR gate for {1, 3, 5, and 7} cycles respectively.

A Write-Buffer Scheme to Protect Cache Memories Against Multiple-Bit Errors

A Write-Buffer Scheme to Protect Cache Memories Against Multiple-Bit Errors

Optimal Caching Policy for D2D Assisted Cellular Networks With Different Cache Size Devices

This paper studies the problem of optimal cache placement to maximize the offloading probability in a device-to-device (D2D) enabled cellular network with small base stations (SBSs). Different from most existing works, we consider unequal users’ equipment (UE) cache memory sizes and all wireless links are modeled as Nakagami-m fading. User preference for each UE and global popularity for SBS, as well as the higher priority of content request from neighboring UEs vs. SBS, are the main factors that make the problem formulation of our work different from that of existing works. It is assumed that each UE caches its desired content with the order of searching its cache, neighboring UEs’ cache via D2D communications, and its serving SBS’ cache. A close to optimal low complexity heuristic cache placement policy is proposed and it is shown that its performance reaches the optimal caching strategy.

CACHE MEMORY FUNCTIONING PRINCIPLES IN HIERARCHICAL COMPUTER SYSTEMS FOR WORKING WITH MULTIMEDIA APPLICATIONS. Part 2, "Электронная техника. Серия 3. Микроэлектроника"

The article provides a preliminary analysis of the organization of a computer memory to develop a method for selecting of optimal cache memory parameters in terms of obtaining the necessary performance, area and power consumption when working with multimedia data.

Critical analysis of cache memory performance concerning miss rate and power consumption

Critical analysis of cache memory performance concerning miss rate and power consumption

Process Tolerant and Power Efficient SRAM Cell for Internet of Things Applications

The use of Internet of Things (IoT) applications become dominant in many systems. Its on-chip data processing and computations are also increasing consistently. The battery enabled and low leakage memory system at subthreshold regime is a critical requirement for these IoT applications. The cache memory designed on Static Random-Access Memory (SRAM) cell with features such as low power, high speed, and process tolerance are highly important for the IoT memory system. Therefore, a process tolerant SRAM cell with low power, improved delay and better stability is presented in this research paper. The proposed cell comprises 11 transistors designed with symmetric approach for write operations and single ended circuit for read operations that exhibits an average dynamic power saving of 43.55% and 47.75% for write and 35.59% and 36.56% for read operations compared to 6 T and 8 T SRAM cells. The cell shows an improved write delay of 26.46% and 37.16% over 6 T and 8 T and read delay is lowered by 50.64% and 72.90% against 6 T and 10 T cells. The symmetric design used in core latch to improve the write noise margin (WNM) by 17.78% and 6.67% whereas the single ended separate read circuit improves the Read Static Noise Margin (RSNM) by 1.88x and 0.33x compared to 6 T and 8 T cells. The read power delay product and write power delay product are lower by 1.94x, 1.39x and 0.17x, 2.02x than 6 T and 8 T cells respectively. The lower variability from 5000 samples validates the robustness of the proposed cell. The simulations are carried out in Cadence virtuoso simulator tool with Generic Process Design Kit (GPDK) 45 nm technology file in this work.

Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time Systems

Modern real-time embedded systems are equipped with multi-core processors to execute computationally intensive tasks. In multi-core architecture, last-level cache memory is shared by cores. The shared cache becomes a non-deterministic resource, which affects the independent execution of real-time tasks. We propose a solution to remedy a variation in execution time when interference happens in a shared cache. Current solutions have relied on memory scheduling approaches that avoid concurrent memory access to guarantee deterministic execution time. However, these methods required complex analysis to accurately estimate the worst-case execution time and to schedule tasks in an overly conservative manner. Unlike existing works, the proposed method prevents simultaneous memory access using the side effect of memory barriers rather than the complicated analysis. A memory barrier is inserted based on a simple code analysis that is performed in units of basic blocks using the LLVM compiler. The proposed method not only does not require the modification of the operating system or task execution flow but also relatively shows fast analysis time. Experimental results show that the proposed basic block-based memory barrier insertion method can reduce the variation in execution time by up to 80% when interference occurs.

Improving Cached Data Offloading Optimization Based on Enhanced Hybrid Ant Colony Genetic Algorithm

The data offloading mechanism is one of the critical strategies needed on edge networks to help cloud computing network performance in serving user data requests. This strategy should be optimized to prevent network congestion. The main problem of this strategy is how to assess the priority of cached data so that the cache memory buffer capacity can be optimized. In this paper, we modeled the cached data offloading strategy using the Knapsack Problem 0/1 (KP01) approach. Several researchers proposed a meta-heuristic algorithm to solve cached data offloading using the KP01 approach. Meta-heuristic algorithms require a reliable solution selection method to find the global optimal solution. However, some studies still use the roulette wheel selection method to provide a set of solutions. The RWS method has a weakness of imbalance the particle fitness with its cumulative probability. Therefore, it is difficult to find the global optimal solution. This study proposed a nested-Roulette Wheel Selection (nRWS) method on hybrid Ant Colony Optimization (ACO) and Genetic Algorithm (GA) to address the cached data offloading optimization using the KP01 approach. The simulation results show that the proposed nRWS method is able to find the global optimal solution in terms of the value of the objective function and hit ratio which is superior to previous studies.

Research on heterogeneous acceleration platform based on FPGA

In the context of today’s artificial intelligence, the volume of data is exploding. Although scaling distributed clusters horizontally to cope with the increasing demands on computing power for massive data processing is feasible. But the unlimited addition of nodes will lead to bloated cluster size. Most of the transistors in CPUs are used to build cache memory and control units, which are not efficient for computing operations of massive data processing. Currently, academia uses hardware devices such as GPU (Graphics Processing Unit), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array) to accelerate deep learning, image processing, which require massive computational operations. The paper first discussed the advantages and technical requirements of FPGA acceleration based on the characteristics of the Spark cluster. Then the paper proposed the design of the FPGA-CPU heterogeneous acceleration platform, and introduced the base-two-FFT algorithm. Finally, the paper present and compared the computation time of the base-two-FFT algorithm before and after the acceleration. The results show that the heterogeneous cluster has a speedup ratio of about 1.79 times compared to the CPU cluster.

Comprehensive Method of Botnet Detection Using Machine Learning

The botnet interrupts network devices and keeps control of the connections with the command, which controls the programmer, and the programmer controls the malicious code injected in the machine for obtaining information about the machines. The attacker uses a botnet to commence dangerous attacks as DDoS, phishing, despoil of information, and spamming. The botnet establishes with a large network and several hosts belong to it. In the paper, the author proposed the framework of botnet detection by using an artificial neural network. The author research upgrades the extant system by comprising cache memory to speed the process. Finally, for detection, the author used an analytical approach, which is known as an artificial neural network, that contains three layers—the input layer, hidden layer, output layer—and all layers are connected to correlate and approximate the results. The experiment result determines that the classifier with 25 epochs gives optimal accuracy is 99.78% and shows the detection rate is 99.7%.

Multi-stream [formula omitted] model and optimization for data prefetching

Modern high-end computing systems, such as storage servers used in Youtube and Tiktok, serve large numbers of concurrent streams, each of which requires aggressive prefetching. This multi-stream prefetching problem, which strives to serve as many requests as possible from the memory cache and minimize response time, remains as an open challenge in computer science research. To address the efficient resource management for data prefetching, this paper introduces a novel method adopted from inventory management of multiple products in operations research. It proposes a unique constrained multi-stream (Q,r) model which simultaneously determines the prefetching degree (order quantity) Q and trigger distance (reorder point) r for each application stream, taking into account the distinct data request rates of the streams. The model has the objective of minimizing the cache miss level (backorder level), which determines the access latency, as well as constraints on the cache space (inventory space) and the total prefetching frequency (total order frequency). Specifically, the disk access time (lead time) is a function of both the prefetching degree and the total prefetching frequency, the latter of which represents the system load. We present the analytical properties of the model, provide numerical optimization examples, and conduct sensitivity analysis to further demonstrate the insights of this prefetching problem. Significantly, an empirical evaluation proves the effectiveness of the prefetching policy provided by our model.

SQLite-CC based on non-volatile memory cache

SQLite-CC based on non-volatile memory cache

Optical RAM Row With 20 Gb/s Optical Word Read/Write

During the past years, optical memories have emerged as the main way to enable fast access times and increased memory bandwidth in synergy with optical interconnections. The migration, however, to fully functional and practical optical RAMs and cache memories will require an additional yet essential step: Optical memories have to get organized into an optical memory subsystem for delivering seamless cooperation between storage and peripheral decoding units, exploiting also the wavelength dimension for efficient RAM architectural layouts. In this paper we demonstrate the first experimentally verified Wavelength Division Multiplexing (WDM) -enabled optical RAM Row subsystem comprising both the peripheral decoding circuitry and a 4-bit optical RAM Row for storing 20Gb/s 4-bit WDM-formatted optical data words. The proposed scheme comprises a single shared multi-λ Semiconductor Optical Amplifier Mach-Zehnder Interferometer (SOA-MZI) Access Gate (AG) for granting access-control to the complete RAM Row, a passive Column Decoder (CD) that directs the incoming WDM-formatted data words to the respective RAM cells that are in turn based on four broadband Indium Phosphide (InP) photonic integrated Flip-Flops (FFs). Our experimental verification firstly investigates the broadband capability of the elementary InP monolithic RAM cell at 5 Gb/s, revealing error-free Write functionality with <4.5 dB power penalty across the whole C-band confirming in this way the potential of efficient scaling to multi-cell WDM-enabled RAMs. Then, experimental validation of the complete 4-bit WDM-enabled optical RAM Row with 20 Gb/s WDM-formatted data words is performed, featuring simultaneous Access gating, decoding and storage operation for all four RAM cells, having a peak power penalty within the range of [4.6-5.6] dB for Write and [2.2-2.9] dB for Read functionalities, respectively, at a Bit Error Rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−9</sup> .

High-performance voltage controlled multilevel MRAM cell

In the recent past, spin-transfer torque (STT) and spin-orbit torque (SOT) based magnetic random access memories (MRAMs) have been studied for future energy efficient and non-volatile memory applications. Multilevel cell (MLC) design has emerged as one of the promising solutions to enhance the storage density of these MRAMs. However, the conventional MLC design adds a larger magnetic tunnel junction (MTJ) stack that makes it difficult to maintain low switching current and high speed. Moreover, it becomes very difficult to reduce the driver transistor size. This paper describes the application of voltage controlled magnetic anisotropy effect to design energy efficient and fast MLC MRAM cell. So far, this approach has been reported only in single-bit MTJ devices. In the proposed MLC the voltage control is able to reduce both SOT and STT switching currents. The results show that the voltage control in MLC enhances energy efficiency and switching speed by more than 80 times and 3 times, respectively, in comparison to conventional SOT based MLCs. The reduction in switching currents also achieves smaller transistor size and enhances area efficiency by 3.5% as compared to conventional SOT-MLC. The effect of different channel materials on SOT switching current has also been explored. Furthermore, the system level evaluation shows that voltage controlled MLC outperforms STT-MRAM and SOT-MRAM for designing cache memory.