Cache Memory Research Articles

Fast Writing Strategy of STT-MRAM With Pipeline Architecture

A fast writing strategy of spin transfer torque (STT) magnetic random access memory (STT-MRAM) combined with pipeline architecture and early write termination (EWT) technology is proposed in this article. Both the writing speed and the writing power consumption of STT-MRAM are optimized. First, based on the proposed pipeline structure, the writing operation can be conducted within a single clock cycle, much decreasing the writing time. Second, the EWT technology is adopted in the writing operation. In the traditional operation of STT-MRAM, the same data are repeatedly written to the memory cell, which wastes the writing power consumption and the writing operation time. In this article, combined with the EWT technology and the pipeline architecture, the unnecessary writing power is reduced by 92.8%, while the necessary writing power is increased by 19.8%. Taking 32 kb data for the writing operation, the operation speed of the new writing strategy is increased by 67.4% compared with the incumbent writing technology. The proposed strategy has potential application in the embedded STT-MRAM acting as cache memory in the computer system.

High-Level Design Optimizations for Implementing Data Stream Sketch Frequency Estimators on FPGAs

This paper presents simple yet effective optimizations for implementing data stream frequency estimation sketch kernels using High-Level Synthesis (HLS). The paper addresses design issues common to sketches utilizing large portions of the embedded RAM resources in a Field Programmable Gate Array (FPGA). First, a solution based on Load-Store Queue (LSQ) architecture is proposed for resolving the memory dependencies associated with the hash tables in a frequency estimation sketch. Second, performance fine-tuning through high-level pragmas is explored to achieve the best possible throughput. Finally, a technique based on pre-processing the data stream in a small cache memory prior to updating the sketch is evaluated to reduce the dynamic power consumption. Using an Intel HLS compiler, a proposed optimized hardware version of the popular Count-Min sketch utilizing 80% of the embedded RAM in an Intel Arria 10 FPGA, achieved more than 3x the throughput of an unoptimized baseline implementation. Furthermore, the sketch update rate is significantly reduced when the input stream is skewed. This, in turn, minimizes the effect of high throughput on dynamic power consumption. Compared to FPGA sketches in the published literature, the presented sketch is the most well-rounded sketch in terms of features and versatility. In terms of throughput, the presented sketch is on a par with the fastest sketches fine-tuned at the Register Transfer Level (RTL).

Enhancing data locality of the conjugate gradient method for high-order matrix-free finite-element implementations

This work investigates a variant of the conjugate gradient (CG) method and embeds it into the context of high-order finite-element schemes with fast matrix-free operator evaluation and cheap preconditioners like the matrix diagonal. Relying on a data-dependency analysis and appropriate enumeration of degrees of freedom, we interleave the vector updates and inner products in a CG iteration with the matrix-vector product with only minor organizational overhead. As a result, around 90% of the vector entries of the three active vectors of the CG method are transferred from slow RAM memory exactly once per iteration, with all additional access hitting fast cache memory. Node-level performance analyses and scaling studies on up to 147k cores show that the CG method with the proposed performance optimizations is around two times faster than a standard CG solver as well as optimized pipelined CG and s-step CG methods for large sizes that exceed processor caches, and provides similar performance near the strong scaling limit.

Proactive Caching in D2D Assisted Multitier Cellular Network.

Cache-enabled networks suffer hugely from the challenge of content caching and content delivery. In this regard, cache-enabled device-to-device (D2D) assisted multitier cellular networks are expected to relieve the network data pressure and effectively solve the problem of content placement and content delivery. Consequently, the user can have a better opportunity to get their favored contents from nearby cache-enabled transmitters (CETs) through reliable and good-quality links; however, as expected, designing an effective caching policy is a challenging task due to the limited cache memory of CETs and uncertainty in user preferences. In this article, we introduce a joint content placement and content delivery technique for D2D assisted multitier cellular networks (D2DMCN). A support vector machine (SVM) is employed to predict the content popularity to determine which content is to be cached and where it is to be cached, thereby increasing the overall cache hit ratio (CHR). The content request is satisfied either by the neighboring node through the D2D link or by the cache-enabled base stations (BSs) of the multitier cellular networks (MCNs). Similarly, to solve the problem of optimal content delivery, the Hungarian algorithm is employed aiming to improve the quality of satisfaction. The simulation results indicate that the proposed content placement strategy effectively optimizes the overall cache hit ratio of the system. Similarly, an effective content delivery approach reduces the request content delivery delay and power consumption.

Cache Coherence issues and Solution: A Review

Computer systems are extensively being used in today’s era and the advancement in computer systems has led to the evolution of various technologies. As the efficiency of the computer systems is to be enhanced, the usage of cache memory becomes a must. The cache memory problems occur when multiprocessor systems are used. When multiple processors are processors share a common memory pool, the problem of cache coherence occurs. Cache coherence is a state in which the cache memories of the processors must stay in coherence with each other. The data should be updated in all the cache systems. Various protocols are used to ensure cache coherence. This study delineates the cache memory architecture, cache coherence, and the issues that arise due to non-consistent data in the cache of multiprocessor systems. Moreover, this study also delineates the protocols of the cache coherence and also describes in detail the MISE protocol. This study will provide an in-depth review of cache, cache coherence, and the issues associated with cache coherence along with the solution.

Blockchain based optimized data storage with secure communication for Internet of Vehicles considering active, passive, and double spending attacks

In the study, we propose a double blockchain based vehicular system for optimizing data storage and securing communication in Internet of Vehicles (IoV) networks. We propose an incentive mechanism and a reputation system to reduce the selfish and distrustful behavior of IoV nodes. Moreover, we propose an encryption technique to protect the proposed system from passive and active attacks. The proposed technique is a hybrid of Rivest Shamir Adleman and Advanced Encryption Standard-256 (AES-256+RSA). We use this hybrid approach to efficiently and secretly share the users' secret keys. To address the issues of high resource consumption and communication delay, we propose a cache memory technique for miner and controller nodes. In addition, we propose an authentication mechanism to remove malicious nodes from the system. The simulation results depict that our system provides security, scalability, optimized data storage, node's trustworthiness, and transparent data sharing.

Low Leakage Low Power Domino Logic Technique for Wide Fan-In Applications, 40-Bit Tag Comparator

Advances in sub-micron technologies make low power consumption and delay a major concern for present day systems. These parameters play a critical role in the performance of most widely used wide fan-in-dynamic logic gates. These wide fan-in dynamic gatesare employed in designing high speed tag comparators which are critical blocks of cache memory. The Stack-Scheme Clocked-Bleeder Domino (SS-CBD)tries to have an insight on a 40-bit tag comparator in terms of power consumption and noise immunity to produce a high-performancelogic style. The approach limits the voltage swing at the dynamic node with the helpof stack transistor employed between dynamic node and clocked bleeder transistor. This technique will reduce the overall power consumption and improves the gate speed for constant noise immunity. The observation is carried out with 1 GHz clock frequency and 0.9 V supply at 27 0C temperature using Cadence Virtuoso Spectre and Layout editor for GPDK 90 nm CMOS technology.

Two-Dimensional Error Correction Code for Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) Caches

Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) is an emerging nonvolatile memory (NVM) technology that can replace conventional cache memory in computer systems. STT-RAM has many desirable properties such as high writing and reading speed, non-volatility, and low power consumption. Since the cache requires a high speed of writing and reading speed, a single-error correction and double error detection (SEC - DED) are applicable to improve the reliability of the cache. However, the process variation and thermal fluctuation of STT-MRAM cause errors. For example, writing ‘1’ bits has more errors than writing ‘0’ bits. We then design the weight reduction code to reduce the error caused by writing ‘1’ bits. Moreover, the performance of an SEC-DED code is improved by constructing an SED-DED code as the product code. The simulation results demonstrate that the two-dimensional error correction code consisting of product code and weight reduction code is roughly 5.67 × 10−4 lower than the SEC-DED code when the error rate of writing ‘1’ bits is equal to 6 × 10−3.

3D Tiled Code Generation for Nussinov’s Algorithm

Current state-of-the-art parallel codes used to calculate the maximum number of pairs for a given RNA sequence by means of Nussinov’s algorithm do not allow for achieving speedup close up to the number of the processors used for execution of those codes on multi-core computers. This is due to the fact that known codes do not make full use of and derive benefit from cache memory of such computers. There is a need to develop new approaches allowing for increasing cache exploitation in multi-core computers. One of such possibilities is increasing the dimension of tiles in generated target tiled code and assuring a similar size of generated tiles. The article presents an approach allowing us to produce 3D parallel code with tiling calculating Nussinov’s RNA folding, i.e., code with the maximal tile dimension possible for the loop nest, executing Nussinov’s algorithm. The approach guarantees that generated tiles are of a similar size. The code generated with the presented approach is characterized by increased code locality and outperforms all closely related ones examined by us. This allows us to considerably reduce execution time required for computing the maximum number of pairs of any nested structure for larger RNA sequences by means of Nussinov’s algorithm.

Error Detection and Correction for Golay Code & Extended Golay Code using Cyclic Redundancy Check

In this paper certain optimization techniques are proposed to reduce the encoder and decoder computation time of cache memory that is affected by soft error and by implementing ECC such as cyclic and block codes. Error that is adjacent by a width of three and two bits are the prime concern of this thesis. Optimised Golay code (23, 12) and new block code size (32, 19) which is also optimised are presented. Nevertheless, cyclic code is efficient compared with block code however, the prime concern of the thesis is to address the triple and double adjacent errors which also includes single bit error, in this regard built-in capability of Golay code is optimised and used for comparison. The extended Golay code is implemented in term of number of slice, number of LUT and maximum combinational path delay compared with existing Golay code.

D2C: Dynamic Decision Caching Mechanism for Provisioning Safety-as-a-Service in Road Transportation

In this article, we propose a dynamic decision caching mechanism (D2C), for provisioning customized safety-related decision to the end users. The end users may be vehicle owners, drivers, or any government organization. Typically, in a safety-as-a-service (Safe-aaS), these end users select certain parameters from the web portal. Based on these selected decision parameters, the decision is provided to them. We consider road transportation as the application scenario of Safe-aaS and design the caching mechanism. In a practical scenario, certain decision parameters such as weather conditions and permissible weight of a vehicle, do not fluctuate with time. Therefore, continuous data transmission, processing, and decision generation consume unnecessary power. The caching of similar decision parameters, which vary slowly with time, is one of the possible solutions. Additionally, the sensor nodes are energy-constrained in nature, hence we take into account these characteristics, delay in delivery of decisions to the end users, and state of end users to propose the dynamic and distributed cache access mechanism. We consider that the edge devices are enabled with cache memory, which results in minimizing the cache access time. Extensive simulation-based analysis of our proposed system, D2C demonstrates that the energy consumption is reduced by 16–53% and cache hit percentage is improved by 28–31%, compared to the existing caching schemes Roy <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et al.</i> (2018), Abdelhamid <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et al.</i> (2015), Abdelhamid <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et al.</i> (2015).

DDR-MRAM: Double Data Rate Magnetic RAM for Efficient Artificial Intelligence and Cache Applications

To reduce the switching delay, area overhead, and power consumption in the magnetic tunnel junction (MTJ)-based memories, this article presents a double data rate magnetic random access memory (DDR-MRAM), which can store information at both clock levels. The proposed memory structure is such that any MTJ type (perpendicular or in-plane) and any switching method can be used as needed. The post-layout simulations based on 40 nm TSMC CMOS technology show that the proposed DDR-MRAM has at least 52% lower write PDP and at least 32% less area-to-maximum input frequency ratio than the conventional MRAMs. Monte–Carlo simulations also confirm the correct and robust operation of the proposed memory in the presence of the inevitable process variation. Moreover, based on the designed DDR-MRAM cell, three architectures are proposed to design <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m\times n$ </tex-math></inline-formula> DDR-MRAM arrays. These architectures are designed and optimized for a specific application, including artificial intelligence (AI) hardware accelerators, high-capacity memory banks, and high-speed cache memories. The simulation results of the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m\times n$ </tex-math></inline-formula> DDR-MRAM arrays show that these arrays offer 100% higher data frequency and at least 28% less area-to-maximum input frequency ratio than the conventional MRAM arrays.

A new parallel algorithm for improving the computational efficiency of multi-GNSS precise orbit determination

The computational efficiency is critical with the increasing number of GNSS satellites and ground stations since many unknown parameters must be estimated. Although only active parameters are kept in the normal equation in sequential least square estimation, the computational cost for parameter elimination is still a heavy burden. Therefore, it is necessary to optimize the procedure of parameter elimination to enhance the computational efficiency of GNSS network solutions. An efficient parallel algorithm is developed for accelerating parameter estimation based on modern multi-core processors. In the parallel algorithm, a multi-thread guided scheduling scheme, and cache memory traffic optimizations are implemented in parallelized sub-blocks for normal-equation-level operations. Compared with the traditional serial scheme, the computational time of parameter estimations can be reduced by a factor of three due to the new parallel algorithm using a six-core processor. Our results also confirm that the architecture of computers entirely limits the performance of the parallel algorithm. All the parallel optimizations are also investigated in detail according to the characteristics of CPU architecture. This gives a good reference to architecture-oriented parallel programming in the future development of GNSS software. The performance of the multi-thread parallel algorithm is expected to improve further with the upgrade of new multi-core coprocessors.s

A Pressure-Aware Policy for Contention Minimization on Multicore Systems

Modern Chip Multiprocessors (CMPs) are integrating an increasing amount of cores to address the continually growing demand for high-application performance. The cores of a CMP share several components of the memory hierarchy, such as Last-Level Cache (LLC) and main memory. This allows for considerable gains in multithreaded applications while also helping to maintain architectural simplicity. However, sharing resources can also result in performance bottleneck due to contention among concurrently executing applications. In this work, we formulate a fine-grained application characterization methodology that leverages Performance Monitoring Counters (PMCs) and Cache Monitoring Technology (CMT) in Intel processors. We utilize this characterization methodology to develop two contention-aware scheduling policies, one static and one dynamic , that co-schedule applications based on their resource-interference profiles. Our approach focuses on minimizing contention on both the main-memory bandwidth and the LLC by monitoring the pressure that each application inflicts on these resources. We achieve performance benefits for diverse workloads, outperforming Linux and three state-of-the-art contention-aware schedulers in terms of system throughput and fairness for both single and multithreaded workloads. Compared with Linux, our policy achieves up to 16% greater throughput for single-threaded and up to 40% greater throughput for multithreaded applications. Additionally, the policies increase fairness by up to 65% for single-threaded and up to 130% for multithreaded ones.

Energy Efficient Dim and Dark Cache for Temperature Reduction of Chip Multiprocessors

Background: For high computation, parallel and distributed processing chip multiprocessors are widely used. In chip multiprocessors, large on chip cache memories are used for performance improvement and speedy execution of the task. These cache memories consume 13% to 45% of the overall power consumed by the entire chip. As chip size shrinks with technology scaling, static energy consumed by the chip increases. This results in heating and chip malfunctioning. To solve this problem we apply static energy reduction techniques to Last Level Cache (LLC) to reduce static energy consumption and thereby chip temperature rise. Methods: Static energy reduction is achieved with two methods. DIM_OLY_SEL Policy:- In this policy, static Energy Reduction is achieved by dimming cache banks. DIM_DARK_PAT Policy:- In this method, dimming as well as darkening techniques are used to save static energy and thereby, temperature reduction. Results: With the implementation of DIM_OLY_SEL policy LLC, Temperature Reduction up to 1.4 Kelvin, improvements in EDP (Energy Delay Product) gains up to 28% and leakage energy Saving up to 23% is observed. With the implementation of DIM_DARK_PAT, we observed LLC temperature reduction up to 4.7 Kelvin, EDP gain improvement of 33 % and leakage energy saving 23%. Conclusion: DIM_OLY_SEL and DIM_DARK_PAT Policies are observed to be very effective policies for energy saving and chip temperature reduction. Hence, they can be used effectively for safe chip multiprocessor functioning.

A Cross-Layer Green Information-Centric Networking Design Toward the Energy Internet

To address the energy-efficiency issue in Information-Centric Networking (ICN), this article proposes a novel Green ICN design, which adapts the power consumption of network nodes to the optimized utilization level proportionally. By learning over the consumers&#x2019; interactive data traffic pattern/behavior, we introduce a new concept of cross-layer power adaption conducted through dynamically adjusting link rate corresponding to content popularity to reduce the wasteful power consumption of Content Routers (CRs). We also develop a controlling policy for each content provider to map its status to the most suitable operating mode to diminish power consumption. Moreover, we propose a smart Selective Caching Scheme (SCS) so that the caching portion in a CR&#x0027;s cache memory is adjusted according to content popularity and available spaces of two customized content cache spaces, namely hot and cold caching queues, for storing popular and unpopular content objects. This scheme can further decrease the power from caching since it is diminished when the traffic load is reduced via the proposed CRs' adaptive mechanism. The evaluation results with practical insights in several distinct scenarios show that the proposal can provide considerably higher energy efficiency and network performance at the same time, typically achieving at least 20&#x0025; power-saving with a higher hop reduction ratio, compared to existing Internet designs with relevant state-of-the-art caching strategies.

Throughput Maximization for Backscatter- and Cache-Assisted Wireless Powered UAV Technology

This paper investigates a wireless powered unmanned aerial vehicle (UAV) communication network with backscatter and caching technologies. Specifically, we assume a self-energized UAV with a cache memory is deployed as a flying backscatter device (BD), term the UAV-enabled BD (UB), to relay the source’s signals to the destination. Whereas the source S can act as a wireless charging station or a base station to supply power or transmit information to the UB using the dynamic time splitting (DTS) method. The UAV utilizes its harvested energy for backscattering (i.e., passive communication) and transmit information (i.e., active communication) to the destination. In this context, we aim to maximize the total throughput by jointly optimizing the DTS ratio and the UB’s trajectory with caching capability at the UB. The formulation is troublesome to solve since it is a non-convex problem. To find solutions, we decompose the original problem into two sub-problems, whereas we first optimize the DTS ratio for a given UB’s trajectory and the UB’s trajectory optimization for a given DTS ratio. By using the KKT conditions, a closed-form expression for the optimal value of the DTS ratio is obtained, greatly reducing the computation time. Moreover, the solution of the second sub-problem can be acquired by adopting the successive convex approximation (SCA) technique. Consequently, an efficient alternating algorithm is proposed by leveraging the block coordinate descent (BCD) method. To show the advantages of the proposed BCD-based algorithm, we also provide the solution of the original problem applying the inner approximation (IA) method. Finally, the intensive numerical results demonstrate that our proposed schemes achieve significant throughput gain in comparison to the benchmark schemes.

MLFTCache: Multilevel Fault Tolerance Scheme for Write-Back L2 Cache Under Irradiation

Cache is prone to soft errors under irradiation, and the incidence rate of multi-bit soft errors in cache memory are becoming larger for modern embedded systems. To improve the cache reliability, we propose a multi-level fault tolerance scheme for write-back L2 cache (MLFTCache). In the workflow of MLFTCache, data bits of cache clean line and dirty line are processed separately. For clean line data bits, 2-way interleaved parity is adopted, and the error is detected and recovered from the next level of memory. For dirty line data bits, the processing is further divided into two layers. The first layer adopts single error correction double error detection (SECDED) code, and the second layer uses multi-bit low redundancy error control with parity sharing (MLREPS) code to detect and correct errors. To reduce the overhead and improve the efficiency of fault tolerance on dirty lines, we adopt two write-back mechanisms. Early write-back mechanism is used to reduce the occurrence of temporal multi-bit soft errors, and emergency write-back mechanism is adopted to deal with the soft error after it is detected. The alpha radiation experiments of Xilinx Zynq-7010 SoC show that cache is prone to multi-bit upsets and the MLFTCache is also dedicated to solving the problem of multi-bit upsets. The cache fault injection and tolerance experiments show that the fault tolerance rate of the MLFTCache proposed in this paper exceeds 90%, while the benchmark schemes are less than 50%. Besides, MLFTCache also has a good performance on dual-core CPU, and its fault tolerance rate on average is 91.34%.

Design and Development of Reconfigurable Cache Memory

Design and Development of Reconfigurable Cache Memory

Flexible use of memory by food-caching birds.

Animals use memory-guided and memory-independent strategies to make navigational decisions. Disentangling the contribution of these strategies to navigation is critical for understanding how memory influences behavioral output. To address this issue, we studied spatial behaviors of the chickadee, a food-caching bird. Chickadees hide food in concealed, scattered locations and retrieve their caches later in time. We designed an apparatus that allows birds to cache and retrieve food at many sites while navigating in a laboratory arena. This apparatus enabled automated tracking of behavioral variables - including caches, retrievals, and investigations of different sites. We built probabilistic models to fit these behavioral data using a combination of mnemonic and non-mnemonic factors. We found that chickadees use some navigational strategies that are independent of cache memories, including opportunistic foraging and spatial biases. They combine these strategies with spatially precise memories of which sites contain caches and which sites they have previously checked. A single memory of site contents is used in a context-dependent manner: during caching chickadees avoid sites that contain food, while during retrieval they instead preferentially access occupied sites. Our approach is a powerful way to investigate navigational decisions in a natural behavior, including flexible contributions of memory to these decisions.