Cache Controller Research Articles

Performance and power effectiveness in embedded processors - customizable partitioned caches

This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural features of modern embedded processors. The automated methodology for. customizing the processor microarchitecture that we propose results in increased performance, reduced power consumption and improved determinism of critical system parts while the fixed design ensures processor standardization. The resulting improvements help to enlarge the significant role of embedded processors in modern hardware-software codesign techniques by leading to increased processor utilization and reduced hardware cost. A novel methodology for static analysis and a microarchitecturally field-reprogrammable implementation of a customizable cache controller that implements a partitioned cache structure is proposed. Partitioning the load/store instructions eliminates cache interference; hence, precise knowledge about the hit/miss behavior of the references within each partition becomes available, resulting in significant reduction in tag reads and comparisons. Moreover, eliminating cache interference naturally leads to a significant reduction in the miss rate. The paper presents an algorithm for defining cache partitions, hardware support for customizable cache partitions, and a set of experimental results. The experimental results indicate significant improvements in both power consumption and miss rate.

WWW Cache Control Mechanism in the AI3 Satellite Network

We propose a WWW cache control mechanism that adapts the traffic of satellite links and latency to retrieve a WWW object for the user. To prefetch a WWW object effectively reduces the latency of a satellite link; however, this technique also generates massive traffic and should be controlled. We use a control mechanism where the rim cache will decide whether to prefetch an object after observing the current traffic of satellite links in real time. The cache then decides which object should be prefetched, based on the users' access patterns. In addition, the hub cache distributes the frequently-accessed objects with multicast transmissions and improves hit ratio on rim caches. We adopted the mechanism for the AI3 satellite network, which connects several research organizations in Asia, and conclude that the proposed system improved the hit ratio of the cache 15% while reducing the mean retrieval time of an object 20%, compared to a conventional cache system.

A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect

This superscalar microprocessor is the first implementation of a 32-bit RISC architecture specification incorporating a single-instruction, multiple-data vector processing engine. Two instructions per cycle plus a branch can be dispatched to two of seven execution units in this microarchitecture designed for high execution performance, high memory bandwidth, and low power for desktop, embedded, and multiprocessing systems. The processor features an enhanced memory subsystem, 128-bit internal data buses for improved bandwidth, and 32-KB eight-way instruction/data caches. The integrated L2 tag and cache controller with a dedicated L2 bus interface supports L2 cache sizes of 512 KB, 1 MB, or 2 MB with two-way set associativity. At 450 MHz, and with a 2-MB L2 cache, this processor is estimated to have a floating-point and integer performance metric of 20 while dissipating only 7 W at 1.8 V. The 10.5 million transistor, 83-mm/sup 2/ die is fabricated in a 1.8-V, 0.20-/spl mu/m CMOS process with six layers of copper interconnect.

Hierarchical, adaptive cache consistency in a page server OODBMS

Due to its simplicity and communication efficiency, many client-server object-oriented database systems are based on the basic page server architecture-pages serve as their smallest unit of data transfer, client caching, and concurrency control. In an earlier paper, we showed how to extend this architecture to permit object-level callback locking, and we showed through simulations that significant performance gains can be expected. In the current paper, we report on our experiences from implementing this approach in the context of the SHORE system. Since SHORE supports multiple lock granularities (volume, file, page, object), we explain how our callback algorithm can be extended to support multigranularity locking. We also discuss some of the stickier issues that arose as we moved our algorithm out of the simulator and into SHORE, which supports a generalized peer-servers architecture. Finally, we present performance measurements that explore the tradeoffs between page-level and object-level concurrency control. Our measurements were obtained by running SHORE on an IBM SP2 shared-nothing parallel machine.

マルチスレッドプロセッサのデータキャッシュ制御方式

In this paper, we present a control method of data cache for a multithreaded processor and its evaluation. A multithreaded processor is effective for 3D-CG, however the increase of the working set size is unavoidable, and this limits the effectiveness of the data cache. Usually, the size and/or the associativity of the cache are increased in order to achieve a higher cache hit rate. This causes the chip size to increase, but the performance remains limited. An inter-thread non-blocking cache control method is proposed for reducing cache miss penalties. This control method achieves higher performance than the blocking cache method and also requires much less hardware cost than a traditional non-blocking cache method. In the case of the proposed cache control method, the performance degradation decreases to half and the performance ratio achieves 80-90% of an ideal cache case.

Simulation Study of a Novel Cache Replacement Algorithm

This work proposes a new scheme for the replacement of cache lines in computer systems. Performance of the proposed algorithm was tested by conducting simulation experiments. Several simulation models were developed for the cache and neural network paradigms. Our simulation engine was driven by traces from the real world workloads/benchmarks. The proposed strategy uses learning properties of non- estimating type of neural networks to understand the replacement phenomenon and guide the replacement decisions made by the cache controller. Therefore, the strategy was successful in being able to eliminate dead lines from the cache memory more efficiently as compared to the conventional algorithms. We observed from the simulation experiments that a well- designed non-estimating neural network- based replacement policy does provide excellent performance as compared to the overwhelmingly used LRU scheme. The new approach can be applied to the page replacement and prefetching algorithms in virtual memory systems.

A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller

This RISC microprocessor is a new, high-performance, PowerPC microprocessor designed specifically for the mobile and high volume desktop personal computer markets. It is an advanced superscalar design with six execution units, aggressive upstream branch processing, out-of-order instruction execution, and a tightly integrated "backside" L2 cache. This dual-issue engine has a four-stage pipeline with dual 32-kB eight-way set-associative L1 caches and an integrated L2 controller with on-chip L2 tag supporting up to 1 MB of external SRAM. A thermal assist unit and an instruction cache throttling mechanism are included for thermal management in mobile applications. A 60X system bus and L2 interface speeds of 100 and 250 MHz are achieved, respectively. This microprocessor achieves workstation class performance (estimated 10 SPECint95 and 9 SPECfp95) while only dissipating 5 W at 250 MHz. The 6.35-million transistor 66.5-mm/sup 2/ die is fabricated in a 2.5-V, 0.3-/spl mu/m, five-layer metal CMOS process.

Designing the MPC105 PCI bridge/memory controller

The MPC105 peripheral component interconnection bridge/memory controller provides a platform-specification-compliant bridge between Power PC microprocessors and the PCI bus. With it, designers can create systems using peripherals already designed for a variety of standard PC interfaces. This bridge chip also integrates a secondary cache controller and high-performance memory controller that supports DRAM or synchronous DRAM and ROM or flash ROM.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

POWER2 fixed-point, data cache, and storage control units

The POWER2™ fixed-point, data cache, and storage control units provide a tightly integrated subunit for a second-generation high-performance superscalar RISC processor. These functional units provide dual fixed-point execution units and a large multiported data cache, as well as high-performance interfaces to memory, I/O, and the other execution units in the processor. These units provide the following features: dual fixed-point execution units, improved fixed-point/floating-point synchronization, new floating-point load and store quadword instructions, improved address translation, improved fixed-point multiply/divide, large multiported D-cache, increased bandwidth into and out of the caches through wider data buses, an improved external interrupt mechanism, and an improved I/O DMA mechanism to support multiple-streaming Micro Channels®.

A Cache coherence protocol for MIN-based multiprocessors

In this paper we present a cache coherence protocol for multistage interconnection network (MIN)-based multiprocessors with two distinct private caches: private-blocks caches (PCache) containing blocks private to a process and shared-blocks caches (SCache) containing data accessible by all processes. The architecture is extended by a coherence control bus connecting all shared-block cache controllers. Timing problems due to variable transit delays through the MIN are dealt with by introducing Transient states in the proposed cache coherence protocol. The impact of the coherence protocol on system performance is evaluated through a performance study of three phases. Assuming homogeneity of all nodes, a single-node queuing model (phase 3) is developed to analyze system performance. This model is solved for processor and coherence bus utilizations using the mean value analysis (MVA) technique with shared-blocks steady state probabilities (phase 1) and communication delays (phase 2) as input parameters. The performance of our system is compared to that of a system with an equivalent-sized unified cache and with a multiprocessor implementing a directory-based coherence protocol. System performance measures are verified through simulation.

Technology application tradeoff studies in multichip systems

This paper presents the results of technology tradeoff studies for multichip systems. Performance analyses which are considered in this study focus on module costs, sizes, and routability, however thermal and electrical performance are also briefly considered. These metrics are influenced by different technology and design approaches including surface and through-hole mounting, wirebond, TAB, and flip chip attach, as well as printed circuit boards, ceramic, and thin film interconnects. Additional design details considered include passive component requirements, thermal structures, and connectors. A number of different modules are considered in the present study, including: a six-chip RISC processor module, a 24-chip RISC processor module with a cache memory, and a few-chip package consisting of a portion of a 80486-based PC motherboard with a cache controller. These examples demonstrate that appropriate technology selections are a function of the design constraints and the components which are packaged, and can not always be inferred from generalizations about the applicability of one technology over another.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A low-cost graphics and multimedia workstation chip set

With just three VLSI parts, Hewlett-Packard's latest workstation class lets designers optimize performance and cost at the system level. Its Hummingbird microprocessor features two-way superscalar execution incorporating two integer units, a floating-point unit, a 1-Kbyte internal instruction cache, an integrated external cache controller, an integrated memory and I/O controller, plus enhancements for little-endian and multimedia applications. Its Artist graphics controller integrates a graphical user interface accelerator, a frame buffer controller, and a video controller on a single chip.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The design of a high-performance cache controller: a case study in asynchronous synthesis

Because of ever-increasing demands on digital system performance, there is a need for new architectures which fully exploit the capabilities of contemporary VLSI technology. Asynchronous or self-timed systems, in particular, promise a number of advantages over traditional synchronous systems: adaptive operation (based on voltage, temperature, process and data), wider environmental operating range, reduced power consumption, and robust interfaces. This paper integrates two distinct areas in asynchronous system design: the design of controllers and the design of processor architectures. In [27], we presented a new method for the synthesis of locally-clocked asynchronous controllers. In [12], the STRiP architecture was shown to provide an attractive alternative to comparable synchronous and asynchronous implementations. However, to support this asynchronous paradigm, an efficient asynchronous memory subsystem is critical. In this paper, we apply the locally-clocked synthesis method to the design of an asynchronous second-level cache controller. The paper contains the following new contributions: (1) it demonstrates the feasibility of the proposed locally-clocked method for the design of a substantial real-world controller; (2) it demonstrates in particular how such a controller can support the asynchronous external interface of an asynchronous RISC architecture (e.g. STRiP); and (3) it presents a cache controller which is significantly faster than a comparable synchronous design. Cache-access latency using our design is 50% less than using an equivalent synchronous implementation.

VIPER: a VLIW integer microprocessor

This paper describes the design and implementation of a very long instruction word (VLTW) microprocessor. The VLIW integer processor (VIPER) contains four pipelined functional units and can achieve 0.25-cycle-per-instruction performance. The processor is capable of performing multiway branch operations, two load/store operations, or up to four ALU operations in each clock cycle, with full register file access to each functional unit. Designed in twelve months, the processor is integrated with an instruction cache controller and a data cache, requiring 450,000 transistors and a die size of 12.9 mm*9.1 mm in a 1.2- mu m technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Revisit the case for direct-mapped chaches

In this paper we argue that a two-way second-level cache is a better design choice than a direct-mapped organization. We show two-way caches are as simple to implement as direct-mapped caches. If the cache controller contains tags, the data array can be organized as a single bank of standard SRAM. Otherwise, both tags and data can be organized as a single SRAM bank. Our simulation results show these novel two-way organizations outperform the direct-mapped approach.

The Mips R4000 processor

The R4000, a highly integrated, 64-b RISC microprocessor that provides a simple solution to the increasing demands on the size of address space while maintaining full compatibility with previous Mips processors, is described. The microprocessor's on-chip central processing unit, floating point unit, memory management unit, primary caches, system interface logic, secondary cache control logic with flexible interface, the programmable system interface for high-performance multiprocessor servers and low-cost desktop systems, the flexible multiprocessor support, and the 1.2 million transistors implemented in CMOS technology are discussed. The R4000's superpipelining techniques allow it to process more instructions simultaneously than the previous generation of microprocessors. It is shown that, according to SPEC benchmark tests, it achieves the highest performance of any microprocessor chip. >

A secondary cache controller design for a high-end microprocessor

The design of a CMOS cache controller chip for a high-end (i486) microprocessor is presented. The cache controller supports either two lines per tag (sectored) or one line per tag (nonsectored). A single cache controller directly supports nonsectored 64 kilobyte or sectored 128 kilobyte cache memories. The sectored mode effectively doubles the cache size compared to the nonsectored mode while maintaining the same tag RAM size. The cache controller is designed to be completely software transparent and contains a 4 K-tag entry tag RAM on-chip and supports burst read, burst line fill, snoop, and back-off cycles. Read-only spaces can also be cached with write protections. Two-way set associativity, sectored cache, and efficient cache protocols optimize performance of the cache memory system and complexity of the cache controller design. This chip supports a 25- or 33-MHz microprocessor. This high speed is achieved by dividing the tag RAM array into eight small sections, thus reducing the overall access time of the tag RAM.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 70‐MHz, 32‐bit BiCMOS processor

AbstractA 70‐MHz, 32‐bit BiCMOS processor has been developed. This paper describes the architecture and the high‐speed technology, mainly the arithmetic unit, of the very‐high‐speed BiCMOS processor. This processor includes a 32‐bit ALU, register file with four ports, arithmetic unit composed of ±32‐bit barrel shifter and so on, ROM storing microprograms, memory management unit, cache controller, and clock generator. The chip integrates 529,000 transistors (including bipolar transistors of 1.5 percent) within 12.98 mm × 12.98 mm chip. The BiCMOS circuit technology is applied to the register file, arithmetic circuit, clock generator, and so on, to achieve the 70‐MHz BiCMOS processor under typical conditions. Thus, the effectiveness of employing the BiCMOS technology for very‐high‐speed digital LSIs, such as microprocessors, has been verified.

Implementation of the PIPE processor

The PIPE (parallel instruction with pipelined execution) processor, which is the result of a research project initiated to investigate high-performance computer architectures for VLSI implementation, is described. The lessons learned from the implementation are discussed. The most important result was the discovery that supporting architectural queues does not complicate the instruction issue logic and fees the processor clock rate from external memory speed influences. It was also found that the decision to support an instruction set with two instruction sizes and to allow consecutive two-parcel instruction issues profoundly affected the instruction fetch logic design. Other significant results concerned the issue logic, barrel shifter, cache control logic, and branch count. >

Computing perspectives: the rise of the VLSI processor

Around 1970 Intel discovered it could put 2,000 transistorsor perhaps a few moreon a single NMOS chip. In retrospect, this may be said to mark the beginning of very large-scale integration (VLSI), ...