マルチスレッドプロセッサのデータキャッシュ制御方式

Abstract

In this paper, we present a control method of data cache for a multithreaded processor and its evaluation. A multithreaded processor is effective for 3D-CG, however the increase of the working set size is unavoidable, and this limits the effectiveness of the data cache. Usually, the size and/or the associativity of the cache are increased in order to achieve a higher cache hit rate. This causes the chip size to increase, but the performance remains limited. An inter-thread non-blocking cache control method is proposed for reducing cache miss penalties. This control method achieves higher performance than the blocking cache method and also requires much less hardware cost than a traditional non-blocking cache method. In the case of the proposed cache control method, the performance degradation decreases to half and the performance ratio achieves 80-90% of an ideal cache case.