Buried Silicon Research Articles

Integration of buried nanomagnet and silicon spin qubits in a one-dimensional fin structure

We adopt a buried nanomagnet (BNM) technology on a one-dimensional (1D) array of silicon spin qubits, and its availability was investigated using numerical simulations. The qubit array is formed in the center of the Si fin and the nanomagnet is buried in the lower lateral part of the qubits. The nanomagnet placed near the qubit generates a strong slanting magnetic field in the qubit, enabling X-gate operation approximately 15 times faster than in conventional cases. Furthermore, the formation of a BNM using a self-aligned process suppresses the dimensional variation of the nanomagnet caused by process variation, thereby mitigating the slanting field fluctuation and fidelity degradation. In addition, even for multiple qubits formed in the Si fin, the BNM with excess length generated a uniform slanting field, mitigating fidelity degradation and enabling all qubits to operate using a single-frequency microwave. Therefore, the proposed structure is useful for 1D integrated structures.

Performance improvement of junctionless SOI-MOSFETs by a superior depletion technique

This work uses a superior depletion technique to present a junctionless silicon-on-insulator (SOI) metal-oxide field-effect transistor (MOSFET) in a 14 nm regime. The suggested technique embeds a P-type area into the buried silicon oxide (SiO2) layer. The p-silicon area has several effects on the proposed structure (EPB-JLSM): First, it helps us attain a full depletion area in the channel. Second, the self-heating improves due to the higher thermal conductivity of silicon than the silicon nitride. Finally, the embedded area causes the lower hole concentration (high Vds at accumulation mode), resulting in a better kink effect. Also, we discuss the impact of inserting the P-silicon area geometry into the buried layer on the DC performance device, such as height and thickness. The P-silicon area decreases the leakage current (IOFF) by three orders of magnitude (∼1000%), and also slightly enhances the drive current (ION) (∼20%), and reduces subthreshold swing (SS) from 186 to 109 mV dec−1 (∼71%) compared to a typical junctionless SOI MOSFET (C-JLSM). Furthermore, we discuss the effect of the buried region and gate insulator materials on the proposed device’s performance.

Application of sensor structures based on a photoelectric transducer to determine the activity of aspartate and alanine aminotransferases in blood plasma

The successful application of a recombination sensor for the real-time detection of transaminasethe detection of transaminase activities (ALT/AST) in the blood plasma of rats has been demonstrated. The parameter directly measured in real time is the photocurrent through the structure with buried silicon barrier when light with high absorption coefficient is used. Detection is realized as a result of specific chemical reactions catalyzed by ALT and AST enzymes (α-ketoglutarate + aspartate and α-ketoglutarate + alanine). The change of the effective charge of the reagents allows recording the activity of enzymes from photocurrent measurements. The main factor in this approach is the influence on the parameters of the recombination centers at the interface. The physical mechanism of the sensor structure can be explained within the framework of the Stevenson theory, taking into account the changes in the pre surface band bending, the capture cross sections and the energy position of the recombination levels during adsorption. The paper also offers theoretical analyze allowing optimization of analytical signals of recombination sensor. A promising approach to develop a simple and sensitive method for real time detection of transaminases activity has been discussed in detail.

Interdigitated Back‐Contacted Carbon Nanotube–Silicon Solar Cells

Carbon/silicon heterojunctions provide a new perspective for silicon solar cells and in particular those made from carbon nanotubes (CNTs) have already achieved industrial‐level power conversion efficiency and device size when using organic passivation and a back‐junction design. However, the current state of the art device geometry for silicon photovoltaics is the interdigitated back contact (IBC) cell and this has yet to be demonstrated for CNT/Si solar cells due to the complexity of fabricating the required patterns. Herein, IBC‐CNT solar cells are demonstrated via the simple spin coating of a conductive hole‐selective passivating film and the evaporation of buried silicon oxide/magnesium electron‐selective contacts for both polarities. The CNT coverage area fraction (fCNT) and the gap between the two polarities are optimized to minimize electrical shading loss and ensure high photocarrier collection. Large‐area (4.76 cm2) highly efficient (17.53%) IBC‐CNT solar cells with a Voc of 651 mV and Jsc of 40.56 mA cm−2 are demonstrated and are prepared with one alignment step for the CNT/Si contact, and photolithographic‐free and room‐temperature processes. These performance parameters are among the best for solution‐processed dopant‐free IBC schemes and indicate the feasibility of using low‐dimensional carbon materials in IBC solar cells.

Introducing a buried pure silicon layer in SOI-MESFET transistor to increase the breakdown voltage by modifying carriers and electric field distribution

Introducing a buried pure silicon layer in SOI-MESFET transistor to increase the breakdown voltage by modifying carriers and electric field distribution

Programmable Parallel Optical Logic Gates on a Multimode Waveguide Engine

Optical logic gates have been proposed and demonstrated on a function programmable waveguide engine constructed using buried silicon nitride waveguides in polymer and a set of thermal electrodes. The device can perform logic AND or OR operations for the input signals A and B, each containing two bits of information, in parallel. The input signals, in the form of binary current values in the electronic domain, are applied to a subset of thermal electrodes, while the computed logic states are converted to optical intensity variations at the single-mode waveguide outputs. The rest of the electrodes work as weights to define the device function, either AND or OR, by adjusting the light interference in the multimode waveguide through thermo-optic effect. Simulations were first performed to reveal the nonlinear response of the received light intensity with respect to the applied current, thus allowing complex and effective manipulation of the light field on the waveguide engine. After chip fabrication and system integration, 65,536 experiments were performed automatically. The data are fed into a sorting program to find the valid settings that satisfy the respective truth table out of the 283,852,800 possible input/weight/output combinations. Four cases of operations for the AND and OR gates are presented in the end, with different bar and contrast values. This simple, low-cost yet powerful engine may be further developed for applications in on-chip photonic computing and signal switching.

The significant role of few sulfite replenishment in boosting electricity generation and organic wastewater degradation in photocatalytic fuel cell

The performance of electricity generation and organic wastewater degradation are two important indicators to evaluate photocatalytic fuel cell (PFC). However, data related to the impact of sulfite, especially few sulfite replenishment on PFC properties are scare. In this paper, a porous sheet-like BiVO4 photoanode was first prepared and then a self-biasing BiVO4-Au/BJS (BJS: buried junction silicon) PFC is constructed. The results show that the BiVO4 film exhibited an optimal water splitting photocurrent density of 1.15 mA cm−2 at 1.23 V vs. RHE. The PFC system can be operated without any external bias and showed high converting performance of organic into electricity. With the total addition of only 2 mM sulfite, a short-circuit current density of 0.61 mA cm−2, which is obviously higher than the BiVO4-Au/BJS system without sulfite, was obtained with maximum power output of 6.5 × 10−4 W cm−2 in 10 mg L−1 methyl orange. Furthermore, a removal ratio of 93.78% after 2 h was achieved with stable current output in the degradation process, compared with the removal ratio of 40.63% without sulfite. More importantly, TOC removal ratio also increased sharply from 30.2% to 85.4%. EPR test demonstrates that radicals including OH and SO4− cogenerated in system.

Substrate Effects on the Bandwidth of CdSe Quantum Dot Photodetectors.

We investigate the time-resolved photocurrent response of CdSe quantum dot (QD) thin films sensitized with zinc β-tetraaminophthalocyanine (Zn4APc) (Kumar , ACS Appl. Mater. Interfaces, 2019, 11, 48271-48280) on three different substrates, namely, silicon with 230 nm SiO2 dielectric, glass, and polyimide. While Si/SiO2 (230 nm) is not suitable for any transient photocurrent characterization due to an interfering photocurrent response of the buried silicon, we find that polyimide substrates invoke the larger optical bandwidth with 85 kHz vs 67 kHz for the same quantum dot thin film on glass. Upon evaluation of the transient photocurrent, we find that the photoresponse of the CdSe quantum dot films can be described as a combination of carrier recombination and fast trapping within 2.7 ns followed by slower multiple trapping events. The latter are less pronounced on polyimide, which leads to the higher bandwidth. We show that all devices are resistance-capacitance (RC)-time limited and that improvements of photoresistance are the key to further increasing the bandwidth.

Surface micromachining of chip-edge silicon microcantilevers using xenon difluoride etching of silicon-on-insulator

We demonstrate a straightforward surface micromachining process for the rapid prototyping of thin ‘chip-edge’ silicon microcantilevers protruding from the edge of a silicon-on-insulator (SOI) chip. The process uses a single photolithographic mask—with xenon difluoride used to both pattern the silicon microcantilevers and release them by etching part of the underlying silicon wafer. During the release step, the silicon microcantilevers are protected from the xenon difluoride by a combination of photoresist and buried silicon dioxide. The use of common microfabrication materials (SOI and positive photoresist) and chemicals (buffered hydrofluoric acid and xenon difluoride), along with a maximum process temperature of 100 °C, makes for a generic, soft micromachining process which is—in principle—compatible with preserving the integrity of any pre-patterned circuitry present on the silicon microcantilever top surface. Doppler vibrometry measurements of the silicon microcantilevers reveal a well-defined resonant frequency and a quality factor comparable with that of similar silicon microcantilevers fabricated using other means. Our enabling technological process allows the rapid prototyping of chip-edge silicon microcantilevers—potentially integrating sensitive circuitry for novel probe technologies—by avoiding the relatively cumbersome, expensive, and potentially circuit-damaging front-to-back processing/deep etching combination.

Optimization of a nanoribbon charge-based biosensor using gateless BESOI pMOSFET structure

Nanoribbons built on gateless (GL) Ultra-Thin Body and Buried Oxide (UTBB) Back Enhanced SOI (BESOI) pMOSFET are analyzed as a charge-based (CB) biosensor for different sensing materials and device’s dimensions. Experimental GL UTBB BESOI pMOSFET are used as a reference structure for the CB biosensor and the influence of different materials and the device’s dimensions are studied by numerical simulations. CB biosensor presents higher sensitivities in weak inversion and for negative charges in the front gate oxide once that, for negative charges, the conduction at the front interface in BESOI pMOSFET is favored. An optimization is performed for negative charges and devices with thicker buried oxide (tBOX = 50 nm) and silicon channel (tSi = 20 nm) are more sensitive, improving the BESOI biosensor’s sensitivity in 14% in weak inversion. The improvement in strong inversion is higher (38%) but the absolute value is three times lower. The nanoribbon GL BESOI pMOSFET showed to be a promising structure for an integrated charged based biosensor, which can be easily fabricated in conjunction with the signal processing circuit.

One Transistor Floating Body RAM Performances on UTBOX Devices Using the BJT Effect

This work aims to analyze through 2D numerical simulations the minimum drain bias for the onset of the parasitic bipolar transistor (BJT) effect (VLatch) of a Ultra-Thin-Buried-Oxide (UTBOX) Fully-Depleted-Silicon-on-Insulator (FDSOI) transistor used as a Single-Transistor-Dynamic-Random-Access-Memory (1TDRAM) cell at high temperatures. The buried oxide thickness (tBOX) and silicon film thickness (tSi) variation were also taken into account and initial studies of the retention time (RT) and the data degradation have been performed. It was verified that the latch voltage, the sense margin current, the latch time and the retention time decrease as the temperature rises.

Novel Si/SiC heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit* *Project supported in part by the Science Foundation for Distinguished Young Scholars of Shaanxi Province, China (Grant No. 2018JC-017) and the 111 Project (Grant No. B12026).

A novel silicon carbide (SiC) on silicon (Si) heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer (PBL Si/SiC LDMOS) is proposed in this paper for the first time. The heterojunction has breakdown point transfer (BPT) characteristics, and the BPT terminal technology is used to increase the breakdown voltage (BV) of Si/SiC LDMOS with the deep drain region. In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region, the p-type buried layer is introduced in PBL Si/SiC LDMOS. The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer, which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance (R on,sp). Through TCAD simulation, when the drift region length is 20 μm, the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS, increased by 77%; And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure, increased by 15%. The figure-of-merit (FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm2 and 6.37 MW/cm2, respectively. For the PBL Si/SiC LDMOS with the drift length of 20 μm, the maximum FOM is 6.86 MW/cm2. The PBL Si/SiC LDMOS breaks conventional silicon limit.

Prediction of the Magnitude of the Trapped Charge in the Buried Oxide of Silicon-on-Insulator Structures Using the Poole–Frenkel Effect

The possibility of predicting the magnitude of the trapped charge in the buried oxide of silicon-on-insulator structures using the Poole–Frenkel effect is investigated. The conditions for the Poole–Frenkel effect in this layer are determined by measuring and modeling the current–voltage characteristics of buried silicon oxide at various temperatures. Processes occurring in the buried oxide when measuring the current–voltage characteristics and during annealing are considered. The conditions of thermal-field treatment of the buried oxide for imitation of the radiation effect using injection are determined. The dependence of the magnitude of the accumulated positive charge in buried silicon oxide due to injection on the Poole–Frenkel current is evaluated. The possibility of applying the Poole–Frenkel effect for evaluating the imperfection of the buried oxide when fabricating microcircuits with increased radiation-dose resistance is shown.

Broadband polarization-insensitive amplitude and phase modulators based on graphene-covered buried and ridge silicon waveguides

In this paper, four easy-to-fabricate graphene-based Si waveguide modulators are presented to overcome the strong polarization dependency of graphene-based modulators. The modulation features of two newly proposed structures, i.e. two graphene-based buried silicon waveguides in addition to two standard ridge silicon waveguides at the telecommunication wavelength of λ=1.55μm are studied. The results show that for certain widths of each waveguide (the height is constant), the amplitude and phase modulations clearly become polarization-insensitive. The amplitude modulation depths for both the TE and TM modes are equal for these optimized waveguides with the precision of 10−3 dB/μm. Moreover, in the proposed modulators, the maximum variations of the real parts of the effective mode indices (EMI) for both the TE and TM modes coincide with each other with an excellent precision (10−4). This precision value is much smaller than the standard criterion value for confirming a polarization-insensitive phase modulation. For proposed structures, the average modulation depth (MD) and maximum variation of the real parts of EMI are about 0.3 dB/μm and 0.02 respectively. Thus, it means to clearly imply small footprints for both amplitude and phase modulations. Furthermore, the performances of all the structures are studied for all optical telecommunication wavelengths. Even without making any changes to the structures designed at 1.55μm at appropriate wavelength intervals, the structures exhibit polarization-insensitive behaviors.

Highly Sensitive 1 × 8 Parallel Multiplexing of Ultra-Compact Integrated 1D Photonic Crystal Sensor Array Based on Silicon-on-Insulator Platform

We design a $1\times 8$ highly sensitive ultra-compact on-chip integrated sensor array consisting of a $1\times 8$ power splitter, eight one-dimensional photonic crystal slot nanobeam cavities (1DPC-SNCs) connected by additional 1D photonic crystal tapered nanobeam bandgap filters (1DPC-TNBF), and an $8\times 1$ power combiner. The performance of the device is numerically demonstrated by three-dimensional finite-difference-time-domain (3D-FDTD) method. The whole structure is lying on top of a $2~\mu \text{m}$ buried silicon oxide layer, while remaining high sensitivities (over 400 nm/RIU) of the eight sensors, simultaneously. The proposed 1DPC-SNCs can reach a high-quality factor of $3.6\times 10^{5}$ . On account of the additional band-stop filters and the $8\times 1$ power combiner, eight sensing segments interrogated simultaneously by one input and one output port is realized, with the ultra-compact footprint of $64\times 16\,\,\mu \text{m}^{2}$ ( $26\times 16\,\,\mu \text{m}^{2}$ in sensing region). Therefore, this design is a promising platform for realizing large-scale photonic integrated circuits with high integration density, especially for ultra-compact multiple on-chip sensing.

Прогнозирование величины захваченного заряда в захороненном оксиде кремния структур кремний-на-изоляторе с применением эффекта Пула-Френкеля

The opportunity to predict trapped charge value in buried silicon oxide of silicon-on-insulator structures using Poole−Frenkel effect was investigated. Using measuring and modeling of current–voltage characteristics of buried silicon oxide at different temperatures conditions for Poole−Frenkel effect in this layer were determined. Processes taking place in buried oxide during measurement of current–voltage characteristics and annealing were considered. Conditions of thermal field treatment of buried oxide for radiation exposure imitation using injection were determined. Dependence of accumulated positive charge value in buried silicon oxide as a result of injection on Poole−Frenkel current value was estimated. The opportunity to use Poole−Frenkel effect for buried oxide defectiveness evaluation during manufacturing of microcircuits with enhanced dose radiation hardness is shown.

Hybrid plasmonic graphene modulator with buried silicon waveguide

We propose a low-loss broadband modulator by combining plasmonic effect with graphene to realize highly efficient modulation on the SOI (Silicon-On-Insulator) platform. Due to a hybrid plasmonic waveguide including buried silicon waveguide and silver waveguides, the fundamental mode is mainly confined in two single-layer graphene sheets, and the electric field vector is parallel to the graphene sheets ensuring the high efficient light absorption of graphene. The specific hybrid structure makes it easy for graphene transfer. Also, non-coplanar structure of silicon waveguide and silver waveguides provides simplified fabrication process and fabrication tolerance. The simulation results demonstrated that modulation bandwidth of 346 GHz is obtained, and the 3 dB modulation length is only 9.493μm. In addition, competitively low propagation loss of 0.85 dB was realized of the hybrid modulator.

Local Isolation of High-Voltage Photovoltaic Cells Using Buried Layers of Oxidized Porous Silicon

In this paper, we have developed a simple method to isolate epitaxially grown thin silicon film using micrometer thick layers of buried porous silicon. The process is based on formation of trenches within epitaxial p-type Si layer that was grown on top of a p+ -type Si (100) wafer. Either electrochemical or galvanic etching in hydro-fluoric solutions procedures were employed to etch the p+ -type silicon under and around the trenches, at the interface of the substrate and the epi-layer, and to transform the etched material into buried PSi. Electrical characteristics of the formed isolation, called “local isolation by buried oxidized PSi”, have been measured. The isolation resistance of the subsequently oxidized PSi film was found to increase by 3-6 orders of magnitude up to the level of few GΩ (GigaOhms). Finally, this procedure has been exploited to demonstrate a miniature photovoltaic solar array where two photovoltaic cells were connected in series using the laser-induced forward transfer metallization process, as a model for high voltage photovoltaic solar cell.

He and O ion implantation induced defects in Si crystal studied using slow positron annihilation spectroscopy

Open volume defect profiles have been obtained in He, O and (He + O) ion implanted silicon crystal 〈1 0 0〉 using slow positron beam measurements. The p-type Si samples have been implanted with He (30 keV), O (120 keV) and both the ions [He (30 keV) + O(120 keV)] with the dose of 1 × 1015 and 1 × 1017 ions/cm2. The average range of these ions in Si is estimated ∼280 nm. The depth dependent defect profiles have also been studied after isochronal annealing (100–900 °C) of the ion implanted Si crystals. On annealing at temperatures (>500 °C), an increase (decrease) in S-parameter was observed in the He (O) ion implanted samples. The variations observed in the S-E profiles indicate that large size open volume defects are created in He irradiated Si followed by annealing at 700 °C. In the case of O and (He + O) implanted samples, variations in S-E and W-E profiles indicate the formation of oxygen-vacancy clusters, a buried silicon oxide layer or oxygen decorated cavities. The S-E (W-E) profiles have been fitted using a program ‘Variable Energy Positron fit’ to evaluate the characteristic S- and W- parameter values of different regions. It is observed through S-W correlation plots that He ions as well as vacancy defects diffuse out of the silicon crystal at higher annealing temperatures. Oxygen-vacancy cluster defects are identified in O implanted (1 × 1015 ions/cm2) and annealed at 700 and 900 °C. In case of O implanted (1 × 1017 ions/cm2) and co-implanted samples (1 × 1015 ions/cm2 and 1 × 1017 ions/cm2) annealed at 700 and 900 °C, formation of oxygen decorated cavities is proposed.

Phase composition of the buried silicon interlayers in the amorphous multilayer nanostructures [(Co45Fe45Zr10)/a‐Si:H]41 and [(Co45Fe45Zr10)35(Al2O3)65/a‐Si:H]41

We consider two amorphous multilayer nanostructures (MLNS) [(Co45Fe45Zr10)/a‐Si:H]41–I and [(Co45Fe45Zr10)35(Al2O3)65/a‐Si:H]41–II that were obtained by ion‐beam sputtering. For determination of the phase composition of the buried amorphous silicon interlayers in these MLNS, we used nondestructive ultrasoft X‐ray emission spectroscopy technique (USXES). The use of the USXES enables to register the silicon Si L2,3–spectra providing the information about the local partial densities of Si s and d occupied states of silicon valence band in silicon‐contained materials. According to the simulation and fitting procedure to the experimental data, Fe3Si and a small amount of oxide (SiO2:H) were found in the interlayer of MLNS‐I. At the same time, the content of silicon dioxides (SiO2) decrease from surface layers to the deep ones. On the other hand, simulation of the phase composition of MLNS‐II reveals the presence of the silicides Fe3Si and Co2Si, oxides SiO2 and SiO1.3, and a small amount of a‐Si:H. The percentage of cobalt silicide Co2Si and suboxide SiO1.3 increased in the deep layers of the MLNS‐II.