Bump Metallization Research Articles

Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

Electro-migration Behavior in Micro-joints of Sn-57Bi solder and Cu Post Bumps

The bonding technique for high density Flip Chip(F.C.) packages requires a low temperature and a low stress process to achieve high reliability of the micro joining. Sn-Bi solder has been noted as a low temperature bonding material. Electromigration behavior of Sn-57wt%Bi flip chip interconnection with Cu post bumps was investigated. The flip chip bumps used for this experiments consisted of Cu post formed with plating and Sn-57wt%Bi solder. Two types of under bump metal(UBM) of organic substrate were studied, that is, electroless Ni(6μm)/Au(0.5μm) on Cu pad and Cu pad. Electron flow to induce the electro-migration was from organic substrate side (Cu pad) to chip side (Cu post) with current density of 40000A/cm2 at 125 degree C. At both types of the UBM, Bi migrated and accumulated to the anode side (Cu post) and Sn migrated to the cathode side (substrate pad). Each interconnect resistance has increased to about 25% and 46% within 100 hours, respectively. However, after more than 3000 hours, they were stabilized. With Ni/Au UBM pad, Cu3Sn/Cu6Sn5 intermetallic compounds (IMCs) were formed at the Cu bump side. And under the Bi layer Cu6Sn5/Ni-Sn compounds were formed. But we didn’t observe the failure like cracks or voids at the Ni layer. With Cu pad, only Cu3Sn IMC at the Cu bump side and under the Bi layer Cu6Sn5/Cu3Sn compounds were formed after 4000 hours. Although the voids were observed at Cu3Sn/Cu interface, good electrical connection was obtained.

Process Development and Reliability of Microbumps

The use of flip-chip bonding technology on gold-tin (AuSn) microbumps for flip-chip packaging is becoming increasingly important in the electronics industry. Some of the main advantages of AuSn system over solder flip-chip technology are suitability for very fine pitch interconnection and fluxless bonding. Fluxless flip-chip assembly is in demand especially for medical applications and optoelectonics packaging. Here, we report the assembly process development of a silicon stacked module assembled with AuSn microbumps to meet the stringent reliability. The effects of bond pressure distribution, bond temperature and alignment accuracy were found to be critical in this stacked silicon using AuSn microbumps. A three-factor design of experiment was carried out to investigate the effects of assembly parameters such as bonding pressure, temperature and time on contact resistance and AuSn solder wetting on the electroless nickel and gold under bump metallization. Results showed that higher bond force is undesirable and contributes to passivation cracking and deformed AuSn joint with AuSn solder being squeezed out of the joint during bonding. The reliability result of the flip-chip assembly of stacked silicon module using AuSn microbumps was presented.

Electroplated indium bump arrays and the bonding reliability

A novel electroplating indium bumping process is described, as a result of which indium bump arrays with a pitch of 100 μm and a diameter of 40 μm were successfully prepared. UBM (under bump metallization) for indium bumping was investigated with an XRD technique. The experimental results indicate that Ti/Pt (300 Å / 200 Å) has an excellent barrier effect both at room temperature and at 200 °C. The bonding reliability of the indium bumps was evaluated by a shear test. Results show that the shear strength of the indium bump significantly increases after the first reflow and then changes slowly with increasing reflow times. Such a phenomenon may be caused by the change in textures of the indium after reflow. The corresponding flip-chip process is also discussed in this paper.

Low-cost bump bonding activities at CERN

Conventional bumping processes used in the fabrication of hybrid pixel detectors for High Energy Physics (HEP) experiments use electroplating for Under Bump Metallization (UBM) and solder bump deposition. This process is laborious, involves time consuming photolithography and can only be performed using whole wafers. Electroplating has been found to be expensive when used for the low volumes which are typical of HEP experiments. In the low-cost bump bonding development work, electroless deposition technology of UBM is studied as an alternative to the electroplating process in the bump size / pitch window beginning from 20 μm / 50 μm. Electroless UBM deposition used in combination with solder transfer techniques has the potential to significantly lower the cost of wafer bumping without requiring increased wafer volumes.A test vehicle design of sensor and readout chip, having daisy chains and Kelvin bump structures, was created to characterize the flip chip process with electroless UBM. Two batches of test vehicle wafers were manufactured with different bump pad metallization. Batch #1 had AlSi(1%) metallization, which is similar to the one used on sensor wafers, and Batch #2 had AlSi(2%)Cu(1%) metallization, which is very similar to the one used on readout wafers. Electroless UBMs were deposited on both wafer batches. In addition, electroplated Ni UBM and SnPb solder bumps were grown on the test sensor wafers. Test assemblies were made by flip chip bonding the solder-bumped test sensors against the test readout chips with electroless UBMs. Electrical yields and individual joint resistances were measured from assemblies, and the results were compared to a well known reference technique based on electroplated solder bumps structures on both chips. The electroless UBMs deposited on AlSi(2%)Cu(1%) metallization showed excellent electrical yields and small tolerances in individual joint resistance. The results from the UBMs deposited on AlSi(1%) metallization were non-uniform and closer inspection revealed micro cracks at aluminum — electroless nickel interface. UBM deposition was also done for Timepix wafers and solder ball placement process was prototyped with 40 μm balls.

Transmission Electron Microscopy Characterization of Ni(V) Metallization Stressed Under High Current Density in Flip Chip Solder Joints

The Ni(V) under bump metallization (UBM) in flip chip solder joints is known to be consumed in a two-stage process during current stressing. The Ni(V) UBM transforms first to the “consumed Ni(V)” state. Then, this consumed Ni(V) transforms to a so-called porous structure. In this study, the details of the consumed Ni(V) and the porous structure were analyzed by transmission electron microscopy. Bright-field images showed that the consumed Ni(V) was a continuous layer without columnar structures and that the porous structure had many voids in the matrix. The compositional analyses showed that V atoms were immobile and trapped in the original Ni(V) layer. Cu and Sn atoms diffused into the original Ni(V) layer, and Ni atoms diffused outward. Selected-area diffraction patterns and high-resolution transmission electron microscopy of the porous structure showed that it was composed of an amorphous matrix with fine crystalline Cu6Sn5 and VSn2 phases.

Impact Testing of Sn-3.0Ag-0.5Cu Solder with Ti/Ni(V)/Cu Under Bump Metallization After Aging at 150°C

Nonmagnetic Ni(V) metal and low consumption rate with solders are the advantages of sputtered Ti/Ni(V)/Cu under bump metallization (UBM). However, a Sn-rich phase (“Sn-patch” herein) can form in the Ni(V) layer after reflow and aging. In lead-free solder, Sn-patches form and grow more quickly than in Sn-Pb solder. Thus, the effect of Sn-patches on solder joint reliability becomes critical. In this study, Sn-3.0Ag-0.5Cu solder was reflowed with Ti/Ni(V)/Cu UBM at 250°C for 60 s, and then aged at 150°C for various durations. A high-speed impact test was introduced to evaluate solder joint reliability. After impact testing, it was found that, the larger the Sn-patch, the greater the propensity of the solder joint to suffer brittle fracture. The correlation between Sn-patch and solder joint reliability is discussed.

Electromigration performance of Pb-free solder joints in terms of solder composition and joining path

The electromigration (EM) performance of Pb-free solder joints is investigated in terms of solder composition (Sn-0.5Cu vs. Sn-1.8Ag) and joining path to Cu vs. Ni(P) under bump metallization (UBM). In the double-sided joints of Ni(P)/solder/Cu, the micro-structure of solder joints and the interfacial intermetallic compound (IMC) layers are significantly affected by solder composition and joining path. The as-reflowed microstructure of Sn-0.5Cu joints consists of small columnar grains with thin IMC layers at both UBM interfaces, independent of the joining path, while Sn-1.8Ag joints have a few large grains of low-angle grain boundaries with thick IMC layers when joined first to Ni(P) UBM, but a few 60° twins with thin IMC layers when joined first to Cu UBM. The EM stressing under high current densities at 150°C reveals that Sn-1.8Ag joints have a superior lifetime compared to Sn-0.5Cu joints. In addition, the EM lifetime of Sn-1.8Ag joints reflowed first on Ni(P) UBM is the longest among four groups of the solder joints examined.

Modeling of electromigration on void propagation at the interface between under bump metallization and intermetallic compound in flip-chip ball grid array solder joints

A void pattern in Sn4Ag0.5Cu solder joints under EM stressing was empirically obtained at the under bump metallization/intermetallic compound (UBM/IMC) interface. The pattern was associated with current crowding and consumption of the UBM layer. A kinetic model was employed and modified to describe the void propagation at UBM/IMC interface. Based on the continuity condition, the void growth velocity was calculated. The analytical results were in good agreement with the experimental data.

Development of indium bumping technology through AZ9260 resist electroplating

Indium bumping is very critical technology in the application of high-density interconnection between a FPA (focal plane array) and a Si ROIC (read-out integrated circuit) by flip-chip bonding. In this paper, the indium BGA (ball grid array) chips are prepared with an electroplating method on the Si substrate. With such a method, the first difficulty arises in removing the seed layer. Two ways, including IBE (ion beam etching) and lift-off, are adopted to overcome it. The results show that the lift-off process is effective but not IBE. During the reflow process, many indium bumps fall off the substrate. Two ways are tried to solve this problem: one is to optimize the reflow profile and the other is to thicken the wetting layer. The results show that these two ways can effectively improve such status. The barrier effects of the UBM (under bump metallization) for indium, which are Ti/Pt (300 Å/200 Å) and Ti/Pt/Au/Ep Au (300 Å/200 Å/1000 Å/4 µm), are also investigated. Experimental results indicate that both of them can be used in application of integration of the FPA and ROIC. Reliability of indium bumps with these two kinds of UBM is evaluated by the shear test. The results show that their shear strength has a significant increase after reflow. For the indium bump with UBM of Ti/Pt/Au/Ep Au (300 Å/200 Å/1000 Å/4 µm), IMC (intermetallic compounds) at the interface of Au–In can strengthen the indium bump but may change the plasticity of indium.

Advanced analysis on board trace reliability of WLCSP under drop impact

Through an aggressive product development program which includes experiment and simulation, Amkor has developed the next level of WLCSP (CSP nl™), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. Failure mechanism of WLCSP under drop test has been established. Depending on type of WLCSP and test board design, three primary failure modes can be observed, i.e. copper (Cu) board trace crack, Cu RDL (redistribution layer) vertical crack and Cu/Under Bump Metallization (UBM) delamination. CSP nl can exhibit distinct failure modes under different test board and/or CSP nl designs, resulting in a vast difference in drop test lifetimes. The primary failure mode is shifted whenever the weakest link is removed through design improvement. This paper will focus on detailed analysis of copper board trace crack under drop test, using an integrated approach of testing, failure analysis, material characterization and modeling. Board design guidelines are formulated to understand the effects of I/O position, board trace routing direction, board trace width, tear drop design, PCB pad size, stack-up thickness, and alloy materials on board trace reliability. Comparison is also made on possible impact on Cu RDL reliability.

Ａｌ‐Ｓｉ合金膜表面のジンケート処理に対する下地Ｓｉ基板の影響

The electrochemical behavior of Al-Si alloy films in zincate solution was investigated to elucidate the effects of zincate pretreatment on the Zn morphology and subsequent electroless NiP deposition, which is used for under bump metallization (UBM) in integrated circuit (IC) chip packaging. To investigate the electrochemical behavior of the Al-Si films during the zincate pretreatment, the immersion potential and the surface morphology during Zn and NiP deposition were evaluated using Al-Si electrodes that had been fabricated onto two types of Si substrates with different specific resistances. A heterogeneous point was observed for samples fabricated onto Si substrates with high specific resistance (45-95 Ωm), but no such point was observed on samples fabricated onto Si substrates with low specific resistance (0.00001-0.00002 Ωm). This result suggests that the morphology of the deposits was affected considerably by the specific resistance of the Si substrate.

Thin Film Packaging Reinforcement for Overmolded MEMS

Thin Film packaging (TFP) is now well known at CEA/LETI and mainly used as a protection for MEMS against degradation which can occur during back end processes: TFP is strong enough to endure the mechanical constraints due to grinding, handling and protects the device from water during the sawing step. Our TFP process is also compatible with under bump metallisation, balling and flip chip processes. The main advantages of our TFP is a very low lost of silicon area, a low cost process with 3 mask levels, and is performed on equipments commonly used in IC fab. In this paper we will speek about process improvement for a TFP overmolded. The thermo-mechanical constraints due to the standard overmolding step (100 bars and 200°C) are much more challenging for TFP: the cavity is about 5 μm high, the cap layer 2μm thick and the polymer plugging layer 6μm thick. So TFP needs to be reinforced to withstand these high constraints. Two processes using conventional IC manufacturing technologies have been developed at wafer level with two materials. 200μm and 500μm wide cavities with TFP were reinforced with these processes and first tested under pneumatically pressure at room temperature: in case of contact between the cap and the substrate, a short circuit is measured between one electrode on the substrate and another electrode behind the cap. Then, the same devices were overmolded at 75 bars and 100 bars at 185°C. In the same run, BAW resonators with TFP and one type of reinforcement were overmolded at 100 bars. The electrical performances of these resonators after overmolding fit very well to the modelling of the test card and are very good. This Compatibility between TFP and overmolding constraints could be a cost effective solution in MEMS packaging.

Electromigration Behavior of through-Si-via (TSV) Interconnect for 3-D Flip Chip Packaging

The electromigration of conventional Sn-37Pb (in mass%) solder bumps was investigated with a current density of 2.0 x 10 4 A/cm 2 at 393 K using three-dimensional (3-D) flip-chip specimens comprised of an upper Si chip and a lower FR-4 substrate. Electromigration failure of the Sn-37Pb solder bumps occurred with complete consumption of electroless Ni immersion Au (ENIG) under bump metallization (UBM) and void formation at the cathode side of the solder bump. Cross-sectional studies were conducted with scanning electron microscopy (SEM). Ni 3 Sn 4 intermetallic compound (IMC) layers were formed in both interfaces, while a typical eutectic structure of Pb- and Sn-rich phases was formed within the solder region. After 11 h current stressing, separation of the Pb- and Sn-rich phases occurred in the solder bump, while a void was formed in the cathode-side bump. After 18 h current stressing, the solder joints catastrophically failed due to the re-melting of the solder bump.

Electromigration Performance of Pb-Free μPILR™ Flip-Chip Packages

The μPILR interconnect is a copper pillar manufactured as a part of a substrate pad. In this paper, we discuss the electromigration (EM) performance of Pb-free μPILR interconnects in a multi-pair daisy chain within 150μm pitch flip-chip packages. Electromigration performance of μPILR interconnects has shown a significant improvement and noticeably delayed electromigration induced failures. Voids initially begin to appear at Cu6Sn5 and solder interface on the die side, with eventual open failure due to excessive void formation along with a severe depletion of Cu Under Bump Metallization (UBM). No failure was observed on the substrate side of the interconnect regardless of the current direction. The enhanced performance of the μPILR interconnect along with other reliability benefits makes it an excellent alternative to conventional solder joints including thin film stack UBMs, thicker copper UBM as well as copper pillar on die.

Detailed Phase Evolution of a Phosphorous-Rich Layer and Formation of the Ni-Sn-P Compound in Sn-Ag-Cu/Electroplated Ni-P Solder Joints

The interfacial microstructure of Sn-3Ag-0.5Cu/Ni-P with various phosphorous contents was investigated by analytical transmission electron microscopy (TEM) and field-emission electron probe microanalysis (FE-EPMA). As the Ni-Sn-P compound was formed between the solder matrix and Ni-P under bump metallization (UBM), the so-called phosphorous-rich layer was transformed to a series of layer compounds, including Ni3P, Ni12P5, and Ni2P. The relationship between Ni-Sn-P formation and the evolution of P-rich layers was probed by electron microscopic characterization with the aid of the Ni-P phase diagram. In addition, the thickness of Ni-P UBM affects the Ni-Sn-P formation. Based on TEM, selected-area diffraction, as well as FE-EPMA, the detailed phase evolution of P-rich layers in the Sn-Ag-Cu/Ni-P joint was revealed. Moreover, in consideration of the mechanical properties of the joint, Ni-Sn-P phase formation, and fabrication feasibility of Ni-P UBM, the phosphorous content and suitable thickness of Ni-P UBM are discussed.

The Effect of Intermetallic Growth on Bump Pull Test Responses of SAC105 Solder Bumps

Cold bump pull tests performed on wafer level chip scale packages using SAC105 solder bumps show an increase in the occurrence of brittle failure modes with aging temperature and time. Fast intermetallic growth at 0–1000 h can be attributed to (Cu,Ni)6Sn5, while the decrease in intermetallic growth rate at t>1000 h can be attributed to diffusion processes leading to (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 formation and growth. Ni diffuses toward the solder bulk and saturates at 175–200°C, while Cu diffuses from the under bump metallization (UBM) toward the solder bump at 125–150°C. Interactions between Cu and Ni atoms lead to saturation of their atomic % gradients due to intermetallic formation. Sn diffusion from the solder toward the UBM occurs at 125–150°C. The activation energy for total intermetallic growth was calculated at 0.2 eV.

Characterization of the Effect of Shape Memory Alloy on Solder Joint Strength Through Modeling and Testing

Currently some of the most common problems that surface mount technology encounters are warpage, delamination, and inelastic strain concentration accumulated in the solder joint during thermal cycling because of mismatch of thermal expansion coefficient between the package and chip side. Material as well as package structure are the critical issues with respect to these problems. The objective of this research is to investigate how shape memory alloy (SMA) applied in the under bump metallization (UBM) can affect solder joint reliability under thermal mechanical stress. Joint strength tests revealed the better strength of solder joints with SMA UBM after accelerated thermal cycling test. Finite element modeling as well as multilayer stress calculations revealed less strain accumulated in the solder and more stress concentrated in Si in the solder joint with SMA UBM. A mechanism by which the SMA accommodates most of the stress and strain caused by the mismatch of the thermal expansion coefficients was proposed to explain the reinforcement of the solder joint by the SMA UBM.

Formation mechanism of Sn-patch between SnAgCu solder and Ti/Ni(V)/Cu under bump metallization

An Sn-patch formed in Ni(V)-based under bump metallization during reflow and aging. To elucidate the evolution of the Sn-patch, the detailed compositions and microstructure in Sn–Ag–Cu and Ti/Ni(V)/Cu joints were analyzed by a field emission electron probe microanalyzer (EPMA) and transmission electron microscope (TEM), respectively. There existed a concentration redistribution in the Sn-patch, and its microstructure also varied with aging. The Sn-patch consisted of crystalline Ni and an amorphous Sn-rich phase after reflow, whereas V2Sn3 formed with amorphous an Sn-rich phase during aging. A possible formation mechanism of the Sn-patch was proposed.

SnAg Microbumps for MEMS-Based 3-D Stacks

Fine pitch 100-mum electroplated SnAg microbump interconnection technology is presented and discussed for use in microelectromechanical systems (MEMS) based 3-D stacks. Electrochemical deposition (ECD) of copper top side metallization (TSM) is compared to performance of nickel-copper TSM on substrate chips. Nickel-copper was selected for under bump metallization (UBM) of die chips. Lead free Sn3.5%Ag was deposited on the die chip UBM and chip-to-wafer bonded by a standard SnAg reflow process in inert atmosphere. An automotive application module was selected as target application for investigating reliability and failure mechanism of the interconnection technology. Bonded units have been investigated by mechanical and physical analysis, visual inspection and electrical resistance measurements after assembly and subsequent environmental stress test including thermal cycling, elevated temperature, humidity, and high current. The fine pitch lead free microbumps displayed promising capability for 3-D stacking of silicon devices. Excellent performance under thermal cycling with no global thermal mismatch was demonstrated. The microbump interconnection technology proved to be tolerant to high temperature and extensive current exposure. TSM consumption and intermetallic compound (IMC) formation were less evident for the nickel-copper TSMs compared to those entirely made of copper. Only minor Kirkendall porosity was observed at the solder alloy interfaces in the present study.