Planar Bulk Research Articles

(Invited) Soft Electrochemical Biosensors and Supercapacitors

In the telehealth and Internet of Things (IoT) context, the development of wearable biosensors has become increasingly necessary to remotely monitor chemical and biological markers anytime, anywhere via a smartphone. To achieve a "burdenless" wearing experience, these devices should ideally be soft and thin, seamlessly integrating with human skin. Electrochemical signal transduction is a promising approach due to its ability to facilitate miniaturization and integration with state-of-the-art technology. However, traditional electrochemical devices, including biosensors and supercapacitors, are often constructed using rigid, planar bulk electrodes with limited electroactive surface areas.In this presentation, I will introduce our innovative skin-like electronic skins and tattoos that utilize standing enokitake mushroom-like vertically aligned gold nanowires as electrochemical electrodes. These soft and three-dimensional electrodes possess high surface areas for efficient electrochemical reactions. Gold is an ideal material due to its biocompatibility, chemical inertness, ease of synthesis/surface functionalization, and band-gap-matching with many semiconductor materials. We will discuss our gold nanowire-based soft biosensing platform in the form of patches, fibers, and tattoos for wireless detection of glucose, lactate, pH, and cationic ions.

Optical Properties of Reactive RF Magnetron Sputtered Polycrystalline Cu3N Thin Films Determined by UV/Visible/NIR Spectroscopic Ellipsometry: An Eco-Friendly Solar Light Absorber

Copper nitride (Cu3N), a metastable poly-crystalline semiconductor material with reasonably high stability at room temperature, is receiving much attention as a very promising next-generation, earth-abundant, thin film solar light absorber. Its non-toxicity, on the other hand, makes it a very attractive eco-friendly (greener from an environmental standpoint) semiconducting material. In the present investigation, Cu3N thin films were successfully grown by employing reactive radio-frequency magnetron sputtering at room temperature with an RF-power of 50 W, total working gas pressure of 0.5Pa, and partial nitrogen pressures of 0.8 and 1.0, respectively, onto glass substrates. We investigated how argon affected the optical properties of the thin films of Cu3N, with the aim of achieving a low-cost solar light absorber material with the essential characteristics that are needed to replace the more common silicon that is currently in present solar cells. Variable angle spectroscopic ellipsometry measurements were taken at three different angles, 50∘, 60∘, and 70∘, to determine the two ellipsometric parameters psi, ψ, and delta, Δ. The bulk planar Cu3N layer was characterized by a one-dimensional graded index model together with the combination of a Tauc–Lorentz oscillator, while a Bruggeman effective medium approximation model with a 50% air void was adopted in order to account for the existing surface roughness layer. In addition, the optical properties, such as the energy band gap, refractive index, extinction coefficient, and absorption coefficient, were all accurately found to highlight the true potential of this particular material as a solar light absorber within a photovoltaic device. The direct and indirect band gap energies were precisely computed, and it was found that they fell within the useful energy ranges of 2.14–2.25 eV and 1.45–1.71 eV, respectively. The atomic structure, morphology, and chemical composition of the Cu3N thin films were analyzed using X-ray diffraction, atomic force microscopy, and energy-dispersive X-ray spectroscopy, respectively. The Cu3N thin layer thickness, profile texture, and surface topography of the Cu3N material were characterized using scanning electron microscopy.

Sensitivity of the thermodynamics of two-dimensional systems towards the topological classes of their surfaces

Using Monte Carlo simulations we study the two-dimensional Ising model on closed manifolds of various topologies near the critical point of the planar bulk system. To this end we consider triangular, square, and hexagonal lattices. We find that the corresponding universal scaling functions of the magnetic susceptibility χ, as well as those of the specific heat C, differ for distinct Euler characteristics K of the manifold. In particular, for each lattice decoration the maxima of the scaling functions of χ grow as K increases. For the specific heat this relationship is inverted: e.g., for each lattice decoration the maxima of the scaling functions of C on the spherical surface (Euler characteristic K=2) is smaller than on the projective plane (K=1) which, in turn, is smaller than on the torus and on the Klein bottle (both with K=0). We find that if the aspect ratio of the lattices is conform to a square geometrical shape, the magnetic susceptibility scaling functions for different lattice types differ only by a non-universal amplitude.

Elastostatics of star-polygon tile-based architectured planar lattices

A panoptic view of architectured planar lattices based on star-polygon tilings was developed. Four star-polygon-based lattice sub-families, formed of systematically arranged triangles, squares, or hexagons, were investigated numerically and experimentally. Finite-element-based homogenization allowed computation of Poisson’s ratio, elastic modulus, shear modulus, and planar bulk modulus. A comprehensive understanding of the range of properties and micromechanical deformation mechanisms was developed. Adjusting the star-polygon angle achieved an over 250-fold range in elastic modulus, over a 10-fold range in density, and a range of -0.919 to +0.988 for Poisson’s ratio. Additively manufactured lattices, achieved by novel printing strategies, showed good agreement in properties. Parametric additive manufacturing procedures for all lattices are available on www.fullcontrol.xyz/#/models/1d3528. Three of the four sub-families exhibited in-plane elastic isotropy. One showed high stiffness with auxeticity at low density and a primarily axial deformation mode as opposed to bending deformation for the other three lattices. The range of achievable properties, demonstrated with property maps, proves the extension of the conventional material-property space. Lattice metamaterials with Triangle-Triangle, Kagome, Hexagonal, Square, Truncated Archimedean, Triangular, and Truncated Hexagonal topologies have been studied in the literature individually. Here, it is shown that these structures belong to the presented overarching lattice family.

Origin of electric field-dependent charge generation in organic photovoltaics with planar and bulk heterojunctions

The electric field dependence in the charge generation process of organic solar cells in planar heterojunction and bulk heterojunction structures is related to the energetics and molecular orientation at the donor/acceptor interfaces.

Diffusion Laws and Modified Pascal’s Triangles

Four main diffusion laws: 1D diffusion in a planar bulk sample or random walks along a straight line x=α1t1/2; 3D diffusion or random walks from a point source and forming small spherical particle: x=α2t1/3; 1D+1D diffusion or random walks along a straight plane with simultaneous outflow into balk: x=α3t1/4; 1D+2D diffusion or random walks along a straight line with simultaneous outflow into balk: x=α4t1/6 are analysed theoretically using mathematical modelling and appropriate physical models. Convex shape of the diffusion profile near the top along a dislocation pipe with simultaneous outflow into balk is predicted. It is shown that the cone angle near the top is increasing with time. Literature experimental data are used for analysis.

Built-in Electric Field for Efficient Charge Separation and Ionic Transport in LiCoO2/SnO2 Semiconductor Junction Fuel Cells

Built-in electric field (BIEF)-induced charge transfer in planar and bulk junctions has significantly improved electrochemical performance in current and advanced energy storage devices such as lithium, sodium, and aluminum batteries. In this study, fuel cells with different junctions based on semiconductor membranes were designed in thin-film planar, bulk planar, and bulk heterojunction (BHJ) configurations to investigate the BIEF effects on their electrochemical performance. These semiconductor membrane fuel cells were constructed with p-type LiCoO2 and n-type SnO2 sandwiched between Ni0.8Co0.15Al0.05LiO2 (NCAL) electrode semiconductors. At 600 °C, the fuel cells with bulk heterojunction (BHJ), bulk planar p–n junction, and thin-film planar p–n junction deliver remarkable peak power densities of 0.82, 0.61, and 0.28 W/cm2 in H2/air operation, respectively. The band structures were determined and the charge transport properties and device operation were investigated. Our results show that the semiconductor membrane-based devices are a good alternative to replace the conventional electrolyte membrane fuel cells for the next generation of fuel-to-electricity conversion technology.

Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs

The dynamic write-access operation in an SRAM has a long-tailed distribution that sets the threshold for write-access failures. The distribution takes a long time to evaluate since rare failure events lie in its long and heavily skewed tail. Moreover, advanced FinFET technologies are becoming increasingly reliant on assist techniques to resolve these rare failures in the tail for improved dynamic performance and stability. In this work, we present various analytical approaches that work well in both super-threshold and subthreshold regions of operation to quickly determine the write-access failure probability. For FinFET based SRAMs, we present a modified sensitivity analysis-based method to evaluate the write-access operation distribution and discuss the evaluation of contention-limited write-access failures. The impact of various write-assist techniques on the performance and stability of FinFET SRAMs is also discussed. All simulations are performed using commercial 65nm bulk planar and 12nm FinFET technologies.

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length.

At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of −0.289 V ± 12.7% and Ioff of less than 10−7 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.

TIARA: Industrial Platform for Monte Carlo Single-Event Simulations in Planar Bulk, FD-SOI, and FinFET

In this article, we present Tool suIte for rAdiation Reliability Assessment (TIARA), an industrial version of a Monte Carlo single-event simulation platform, enabling fast and accurate soft error rate (SER) estimations. This tool is capable of simulating logic cells manufactured in several technologies such as fully depleted silicon on insulator (FD-SOI), FinFET, and planar bulk CMOS. Moreover, TIARA is able to handle many different types of radiations including by-products of neutron or proton spallation, heavy ions and alpha particles, representative of terrestrial and space environments. Three use cases are shown in this article to illustrate TIARA capabilities. The first one compares the error rate in Geostationary Earth Orbit (GEO) orbit of all flip-flop variants from a 28-nm FD-SOI library. Second one evaluates multiple-cell upsets as a function of simulated array size for static random access memory (SRAM) cells manufactured in a 40-nm bulk technology. The last one shows alpha and neutron SER results for SRAM designed in a bulk-FinFET technology.

Defects in Hard Carbon: Where Are They Located and How Does the Location Affect Alkaline Metal Storage?

Hard carbon anodes have shown significant promise for next-generation battery technologies. These nanoporous carbon materials are highly complex and vary in structure depending on synthesis method, precursors, and pyrolysis temperature. Structurally, hard carbons are shown to consist of disordered planar and curved motifs, which have a dramatic impact on anode performance. Here, the impact of position on defect formation energy is explored through density functional theory simulations, employing a mixed planar bulk and curved surface model. At defect sites close to the surface, a dramatic decrease ( 50%) in defect formation energy is observed for all defects except the nitrogen substitutional defect. These results confirm the experimentally observed enhanced defect concentration at surfaces. Previous studies have shown that defects have a marked impact on metal storage. This work explores the interplay between position and defect type for lithium, sodium, and potassium adsorption. Regardless of defect location, it is found that the energetic contributions to the metal adsorption energies are principally dictated by the defect type and carbon interlayer distance.

Electrostatic tip effects in scanning probe microscopy of nanostructures

Electrical scanning probe microscopies (SPM) use ultrasharp metallic tips to obtain nanometer spatial resolution and are a key tool for characterizing nanoscale semiconducting materials and systems. However, these tips are not passive probes; their high work functions can induce local band bending whose effects depend sensitively on the local geometry and material properties and thus are inherently difficult to quantify. We use sequential finite element simulations to first explore the magnitude and spatial distribution of charge reorganization due to tip-induced band bending (TIBB) for planar and nanostructured geometries. We demonstrate that tip-induced depletion and accumulation of carriers can be significantly modified in confined geometries such as nanowires compared to a bulk planar response. This charge reorganization is due to finite size effects that arise as the nanostructure size approaches the Debye length, with significant implications for a range of SPM techniques. We then use the reorganized charge distribution from our model to describe experimentally measured quantities, using in operando scanning microwave impedance microscopy measurements on axial p-i-n silicon nanowire devices as a specific example. By incorporating TIBB, we reveal that our experimentally observed enhancement (absence) of contrast at the p-i (i-n) junction is explained by the tip-induced accumulation (depletion) of carriers at the interface. Our results demonstrate that the inclusion of TIBB is critical for an accurate interpretation of electrical SPM measurements, and is especially important for weakly screening or low-doped materials, as well as the complex doping patterns and confined geometries commonly encountered in nanoscale systems.

Extraction of Mobility Degradation and Source-and-Drain Resistance in MOSFETs

A MOSFET model parameters extraction procedure that overcomes the difficulties of separating the effects of source-and-drain series resistance and mobility degradation factor is presented. Instead of the conventional direct fitting, the present procedure involves the use of indirect bidimensional fitting of the source-to-drain resistance of a single device, as obtained from the below-saturation output characteristics measured at several above-threshold gate voltages. The procedure is verified with a simulated long channel FinFET device with externally added resistances and is later applied to experimental planar bulk DRAM MOSFET devices with channel lengths ranging from 0.23μm to 2.0μm. The procedure is shown to be advantageous in terms of computational efficiency and it is appropriate even with high values of externally added series resistances. For the case of devices with various channel lengths, the accuracy of the procedure is improved if the value of RSD is extracted from the shortest channel length. This value of RSD could be used for extracting the other parameters for devices with longer channel.

High-Power Generation for mm-Wave 5G Power Amplifiers in Deep Submicrometer Planar and FinFET Bulk CMOS

A review is presented of the key techniques for high-power, high-efficiency millimeter-Wave (mm-Wave) 5G power amplifier (PA) design in deep submicrometer planar and FinFET bulk CMOS processes. The work utilizes a distributed unit cell-based layout technique for neutralized differential pairs and stacking transistors in bulk CMOS. This article also proposes a prediction of saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) and its corresponding maximized power-added efficiency (PAE) at 39 GHz for three candidate power combined architectures of three-stage PAs with two supporting prototype PAs fabricated in 16-nm FinFET and 28-nm planar bulk CMOS processes. The single-stage two-stack 16-nm FinFET PA generates a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 18.3 dBm from a 1.8-V supply at 39 GHz with a drain efficiency (DE) of 35.5%. The three-stage 28-nm PA incorporates a two-stack output stage with a balanced and compact 4-to-1 series-parallel combiner and achieves a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 26 dBm using a 2.2-V supply, PAE of 26.6%, and high average power measurements with single-carrier and 5G new radio orthogonal frequency-division multiplexing modulations with competitive efficiencies. Long-term reliability measurements are performed using aging acceleration techniques to demonstrate the robustness of both prototypes. The competitive power and efficiency results, supported with reliability measurements, show that bulk CMOS can achieve performance comparable to SOI CMOS for generating high power at mm-Wave frequencies.

Engineering substrate doping in bulk planar junctionless transistor: Scalability and variability study

In this work two dimensional sentaurus simulations are used to study the impact of substrate doping on scalability and the variability of the bulk planar junctionless transistor (BPJLT). The results shows that, although increasing substrate doping density in BPJLT reduces the off-state current, subthreshold slope and the drain induced barrier lowering, the on-state current of the device is almost constant. To improve digital logic circuit performance of nanoscale BPJLT, novel δ-layer BPJLT (δ-BPJLT) is being proposed by incorporating p-type δ- layer below the uniformly doped device layer containing source, channel and the drain regions of BPJLT. It has been found that, the δ-layer below the device layer leads to reduction in the off-state current, process induced variability and the short-channel effects of the BPJLT. This is mainly because of the screening effect due to δ-layer under the device layer which significantly reduces the variations induced because of random dopant fluctuations.

Fundamental limits to attractive and repulsive Casimir-Polder forces

We derive upper and lower bounds on the Casimir--Polder force between an anisotropic dipolar body and a macroscopic body separated by vacuum via algebraic properties of Maxwell's equations. These bounds require only a coarse characterization of the system---the material composition of the macroscopic object, the polarizability of the dipole, and any convenient partition between the two objects---to encompass all structuring possibilities. We find that the attractive Casimir--Polder force between a polarizable dipole and a uniform planar semi-infinite bulk medium always comes within 10% of the lower bound, implying that nanostructuring is of limited use for increasing attraction. In contrast, the possibility of repulsion is observed even for isotropic dipoles, and is routinely found to be several orders of magnitude larger than any known design, including recently predicted geometries involving conductors with sharp edges. Our results have ramifications for the design of surfaces to trap, suspend, or adsorb ultracold gases.

(Keynote) Fully-Depleted SOI Technology for High-Power RF Applications

FDSOI has shown its benefits, compared to other planar bulk technologies, in low power applications by a better electrostatic control, a reduction in leakage currents and device variability. Thanks to the isolation box in the substrate and the intrinsic channel, the parasitic capacitances are also reduced significantly, including the capacitance between source and drain, and between drain and body. These features help to boost the transistors’ RF performance. The published data shows the measured fT (cut-off frequency) and fMAX (maximum oscillation frequency) of RFMOS in FDSOI processes reach 400 GHz, which is the highest among all advanced CMOS nodes. Moreover, by the process construction (gate-first vs. gate-last), the gate resistance of the transistors in FDSOI processes is smaller, which is beneficial to their RF noise performance. These benefits have been used for small-signal RF blocks in Front-end modules, e.g. LNA, VCO and mixers.In this work, the FDSOI capability for the large-signal RF blocks consisting of integrated power amplifiers (PA) is explored. In previous mobile generations (3G/4G), the base stations need to deliver the peak power more than 100 W, which is solely enabled by GaN or GaAs technologies. Their corresponding handsets also need to transmit a few Watts, which is out of the reach of CMOS-based PA. By moving to massive MIMO with a large number of antennas, the power per RF PA is reduced significantly for both base-stations and handsets in 5G network, with the PMAX per PA varying from 20 dBm to 25 dBm. Such sub-Watt power range opens the opportunities for making silicon-based RF PA, enabling a much larger scale of RF Front-end modules integration. In this paper, two key aspects to make the FDSOI process possible for high-power RF applications in 5G are presented. First, it shows the development of critical active and passive components of high-breakdown and high RF-performance. Second, the 4-port RF test structure designs and in-house characterization to explore the capability of back-bias on RF performance are discussed.Regarding the high-voltage transistors, 3.3V and 5V RF LDMOS have been designed and fabricated without any additional dedicated mask in a sub-28nm FDSOI process. The device was constructed in a non-SOI area. A record high RF-performance, with fT larger than 50 GHz for 5V LDMOS and 100 GHz for 3.3V device, has been achieved. For passive elements, 7V fringe capacitators, inductors and transformers have been developed. The fringe capacitors show their robustness at 7V, with best-in-class quality factor at both 5 GHz and 30 GHz. The matching performance of these capacitors are comparable to the best MOM capacitor mismatch performance in other modern CMOS technologies, which makes them also suitable for high-precision signal processing and filtering. Inductors and transformers have been designed in top 3 metal layers to have state-of-the-art quality factors. An excellent matching between RF measurements and EM simulations has been obtained for these passive elements. Such matching proves that the performance of the passive devices is very well predictable, enabling full design optimization for fringe capacitors and transformers / inductors.To capture the impact of back-bias on RF performance, and facilitate the RF model against silicon validation in the presence of back-bias, this paper shows a 4-port test structure design (GSGSG). The RF measurements for an RFMOS with a back-bias varying from strong reverse to forward are discussed. These results initiate various scenarios for using back-bias in RF applications, e.g. reducing the supply voltage to have the same RF performance, or extending the maximum current density at the same peak fT to have enough RF power.In summary, this paper shows the development of high-voltage RF active and passive devices in a sub-28nm FDSOI process, which are required for building integrated RF power amplifiers at Watt-level in high-performance cost-effective RF front-end ICs. The 3.3V / 5V RF-LDMOS with a cutoff frequency beyond 100GHz has been achieved in silicon, which brings a breakthrough for RF PA designs, both at sub-6GHz and 28GHz. For passive devices, by combining the novel RF design with an RF-compatible metal stack and accurate EM simulation, a record high Q-factor for a 7V-fringe capacitor, a 2-way transformer and 8-shaped inductors are obtained. The developed 4-port measurement for GSGSG structures has been proven as an indispensable tool for RF-FDSOI. These results show FDSOI process can be comparable to RF-HV-centric non-CMOS processes, e.g. SiGe and GaAs, for Watt-level power RF applications.

A study of damage-free in-situ etching of GaN in metalorganic chemical vapor deposition (MOCVD) by tertiarybutylchloride (TBCl)

Abstract This paper reports a study of the effect of NH3 flow rate and reactor temperature on the tertiarybutylchloride (TBCl) etching of patterned GaN-on-sapphire templates. It is found that a reduced NH3 flow rate and an elevated reactor temperature can eliminate islands or dots on the surface, while at the same time, enhance the etching around dislocations. TBCl etching was also performed on planar bulk GaN templates with much lower dislocation density. We find an atomically flat and layer-by-layer etching behavior within the region free of dislocations. Surface kinetics analysis reveals a short diffusion length of etching products. Room-temperature photoluminescence (PL) and x-ray photoelectron spectroscopy (XPS) measurements confirm that TBCl etching is capable of removing the damage and impurities induced by plasma etching without introducing additional damage.

Random telegraph noise in gate-all-around silicon nanowire MOSFETs induced by a single charge trap or random interface traps

The random telegraph noise (RTN) in gate-all-around (GAA) silicon (Si) nanowire (NW) metal–oxide–semiconductor field-effect transistors (MOSFETs) induced by a single charge trap (SCT) or random interface traps (RITs) is studied for the first time. An experimentally validated three-dimensional quantum-mechanically-corrected device simulation is advanced to investigate the explored devices. The magnitude of the RTN decreases with increasing gate voltage to different extents for the planar MOSFET, bulk FinFET, and GAA Si NW MOSFET devices, owing to the reduction in the conducting carriers along the channel. For the GAA Si NW MOSFET, the reduction of the fluctuation of threshold voltage in the presence of RITs is about 25 and 3 times when compared with the planar MOSFET and bulk FinFET device, respectively, whereas this reduction in the presence of an SCT is about 6 and 2.6 times, respectively. For the GAA Si NW MOSFET, the reduction of the RTN in the presence of RITs is about 7.5 and 4.7 times when compared with the planar MOSFET and bulk FinFET device, respectively, whereas this reduction in the presence of an SCT is about 22 and 6 times, respectively. At given threshold voltage, compared with the results for the planar MOSFETs and bulk FinFET, the GAA Si NW MOSFET exhibits minimal characteristic variability and RTN owing to the ultimate electrostatic control of the gate from the point of view of electrostatic integrity.

NCFET-Based 6-T SRAM: Yield Estimation Based on Variation-Aware Sensitivity

The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS) < 60 mV/decade at 300 K. In this work, the n-type NCFET (i.e., pull-down (PD) and passgate (PG) transistor in six-transistor (6T) SRAM bit-cell) has SS of 53.92 mV/decade, and the p-type NCFET (i.e., pull-up (PU) transistor in the 6T SRAM bit-cell) has SS of 58.96 mV/decade. In the NCFET-based SRAM cell (vs. conventional SRAM cell with conventional planar bulk MOSFETs), its read (hold)-stability and write-ability are evaluated by the metric of read static noise margin (SNM) and write-ability current (Iw), respectively. Then, under process-induced random variation, sensitivities of SNM and Iw are extracted. Finally, the yield of NCFET-based SRAM array (vs. conventional SRAM array) is quantitatively estimated using the cell-sigma.