Built-in Self-test Research Articles

Research on the Built-in Test Design of Civil Aircraft Flight Control System

Abstract Based on ARINC 624 for civil aircraft airborne maintenance system, the working modes and application forms of civil aircraft Flight Control System Built-in Test (BIT) design are given. The test principles and implementation methods of the civil aircraft Flight Control System Power-on BIT and Initiated BIT are analyzed in detail, and the overall functional architecture of the civil aircraft Flight Control System BIT is described. Taking the actuator as an example, the realization method of its return to service test is analyzed. Finally, the general characteristics of the BIT technology of the civil aircraft Flight Control System are summarized.

Adaptation of of March-SS algorithm to word-oriented memory built-in self-test and repair

<span lang="EN-US">The technology shrinkage and the increased demand for high storage memory devices in today’s system on-chips (SoCs) has been the challenges to the designers not only in the design cycle but also to the test engineers in testing these memory devices against the permanent faults, intermittent and soft errors. Around 90% of the chip area in today’s SoCs is being occupied by the embedded memories, and the cost for testing these memory devices contributes a major factor in the overall cost and the time to market. This paper</span><span lang="EN-US">proposes a strategy to develop a word-oriented March SS algorithm-basedmemory built-in self-test (MBIST), which is then applied for memory built-in self-test and repair (MBISTR) strategy. The implementation details for 1 KB of single-port static random-access memory (SRAM) depict that the modified March-SS algorithm based MBISTR-enabled SRAM facilitates self-test and self-repair of embedded memories with a marginal hardware overhead (<1%) in terms of look up tables and slice registers when compared to that of standard SRAM.</span>

Power analyzer of linear feedback shift register techniques using built in self test

Wasteful patterns that don't lead to fault dropping squander a tone of energy in the linear-feedback shift register and circuit under examination in a random research region. Random switching actions in the CUT and scan pathways between applications with two consecutive vectors are another significant cause of energy loss. This study proposes a unique built-in self-test (BIST) technique for scan-based circuits that might help save energy. Only the available vectors are produced in a fixed series thanks to a mapping logic that alters the LFSR's state transitions. As a consequence, and without reducing fault coverage, the time it takes to execute trials has decreased. Experiments on circuits demonstrated that during random testing, the linear feedback shift register saves a significant amount of power.

On the Use of Acoustic Methods for the Detection of Electrostatic Capture of Diaphragm in Capacitive MEMS Microphones

Most mobile phones today have capacitive micro-electro-mechanical systems (MEMSs) microphones that use either single or dual diaphragms. Methods to detect failures easily and non-invasively have become of critical importance for microphones mobile phone manufacturers as a basis for built-in self-test (BIST) and self-repair (BISR) strategies. In that regard, a four-layer framework is presented that includes lumped element modeling (LEM), failure mode simulation, failure mode discrimination, and recovery. The frequency response of the microphone is taken as the main output to analyze. To experimentally validate this framework, this article provides a failure mode induction method based on bias voltage sweeping and four new techniques, based solely on acoustic measurements to discriminate the states of electrostatic capture for single diaphragm capacitive MEMS microphones. These include 1) analysis of an acoustic signature that is unique to electrostatic capture based on cosine similarity analysis; 2) −3 dB point measurement; 3) +3 dB point measurement; and 4) cluster analysis. Measurement of pull-in voltage and snapback voltage ranges is further demonstrated based on sensitivity measurements in laboratory conditions and response magnitude and noise power measurements in non-laboratory conditions. Up to 100% success rate in detecting electrostatic capture of diaphragm is reported for this type of device.

Co-design of a Smartphone App for People Living With Dementia by Applying Agile, Iterative Co-design Principles: Development and Usability Study.

BackgroundThe benefits of involving those with lived experience in the design and development of health technology are well recognized, and the reporting of co-design best practices has increased over the past decade. However, it is important to recognize that the methods and protocols behind patient and public involvement and co-design vary depending on the patient population accessed. This is especially important when considering individuals living with cognitive impairments, such as dementia, who are likely to have needs and experiences unique to their cognitive capabilities. We worked alongside individuals living with dementia and their care partners to co-design a mobile health app. This app aimed to address a gap in our knowledge of how cognition fluctuates over short, microlongitudinal timescales. The app requires users to interact with built-in memory tests multiple times per day, meaning that co-designing a platform that is easy to use, accessible, and appealing is particularly important. Here, we discuss our use of Agile methodology to enable those living with dementia and their care partners to be actively involved in the co-design of a mobile health app.ObjectiveThe aim of this study is to explore the benefits of co-design in the development of smartphone apps. Here, we share our co-design methodology and reflections on how this benefited the completed product.MethodsOur app was developed using Agile methodology, which allowed for patient and care partner input to be incorporated iteratively throughout the design and development process. Our co-design approach comprised 3 core elements, aligned with the values of patient co-design and adapted to meaningfully involve those living with cognitive impairments: end-user representation at research and software development meetings via a patient proxy; equal decision-making power for all stakeholders based on their expertise; and continuous user consultation, user-testing, and feedback.ResultsThis co-design approach resulted in multiple patient and care partner–led software alterations, which, without consultation, would not have been anticipated by the research team. This included 13 software design alterations, renaming of the product, and removal of a cognitive test deemed to be too challenging for the target demographic.ConclusionsWe found patient and care partner input to be critical throughout the development process for early identification of design and usability issues and for identifying solutions not previously considered by our research team. As issues addressed in early co-design workshops did not reoccur subsequently, we believe this process made our product more user-friendly and acceptable, and we will formally test this assumption through future pilot-testing.

BIT-Based Intermittent Fault Diagnosis of Analog Circuits by Improved Deep Forest Classifier

In order to reduce the high built-in test (BIT) false alarms of analog circuits caused by intermittent faults, a BIT based intermittent fault diagnosis method for analog circuits by improved deep forest (DF) classifier is proposed. Firstly, the local mean decomposition and multi-scale entropy (LMD-MSE) are employed for multi-scale time-frequency analysis since it can handle the data nonlinearity and eliminate redundant information. Secondly, the particle swarm optimization (PSO) algorithm is adopted in optimizing the multi-scale factors to form the feature sets. Then, the feature sets are used to train the DF classifier and the intermittent faults of the analog circuits are diagnosed by the classifier. Meanwhile, in order to improve the diagnostic accuracy of the DF classifier for intermittent faults, the classifiers of each level of DF are replaced by extreme random forests and rotation forests. The optimized characteristic of DF improves the diagnosis accuracy and can locate the intermittent faults to the circuit branch with intermittent faults. The method is evaluated with the four-opamp biquad high-pass filter circuit. Compared with other common methods, it is shown by the given extensive comparative experiment test results that the proposed approach has achieved better diagnostic results, exhibiting greater advantages in intermittent fault diagnosis with small sample data.

A Modified PRBS: Vertical Stacked LFSR Primitive Polynomial for Secure Data Communication

Linear Feedback Shift Register (LFSR) generates the fault coverage test patterns to compute the target fault of data compression methods. Future Generation wireless communication covers irrespective of complex situation and dense environments marginable throughput to everyone. LFSR widely applied to generate Pseudo Random Noise Sequence, Digital Random Number Generator commonly employed in Cryptography, encoding techniques, Built in Self-Test (BIST) etc. Sequence generated by the LFSR are easily predictable as periodic nature of the sequence. A Modified Pseudo Random Sequence Generator (PRBS) with vertical stacked LFSR (VS-LFSR) is proposed to improve security against predictability nature of PRBS. The primitive polynomial of the nbit LFSR is vertically stacked with top most polynomial and ends with the least polynomial with this flexible of the primitive polynomial are processed and Random sequences are generated. The proposed method generates the random numbers of flexible ranges by appropriately selecting necessity primitive polynomial code in the vertical stack. Compare to conventional LFSR, all zero (0) states also generated in the VS-LFSR, enables the test pattern to have all 2npossible states of n-bit LFSR. With little hardware complexity, periodic pattern of LFSR is further improved with the maximum number of states and result attained maximum number of random outputs as Πn-202n-m - 1.

Design of a Cost-Efficient Monostatic Radar Sensor With Antenna on Chip and Lens in Package

This work presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}$ </tex-math></inline-formula> -band monostatic radar system operating from 144.6 to 161 GHz, which is placed inside a 3-D-printed low-cost case with a built-in lens to boost the antenna (ANT) directivity. The monolithic microwave integrated circuit (MMIC) is manufactured in a 130-nm BiCMOS process and includes a compact transceiver architecture consisting of an oscillator, a diode-based mixer, and an on-chip antenna. The implemented topology allows to significantly improve the signal-to-noise ratio and features a built-in self-test (BIST) structure with the possibility to provide on-chip antenna characterization using power sensors in combination with a directional coupler. Housed inside the robust printed package, the MMIC has only dc and baseband frequency connections, which offers ease of handling and poses the low-cost potential for a variety of applications. The complete transceiver chip consumes only 84.7 mA from a 3.3-V supply and its size is 1964 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times1448\,\,\mu \text{m}$ </tex-math></inline-formula> . Together with the package the sensor measures a size of 42.2 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times42.2$ </tex-math></inline-formula> mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times45.7$ </tex-math></inline-formula> mm.

Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS

Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phase-locked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \!\Sigma $ </tex-math></inline-formula> loop is validated. The entire BIST system consumes 0.6mW with a system self-calibration algorithm to tackle the analog blocks’ nonlinearities.

An Efficient and Reliable Chaos-Based IoT Security Core for UDP/IP Wireless Communication

The ultimate focus of this paper is to provide a hyperchaos-based reconfigurable platform for the real-time securing of communicating embedded systems interconnected in networks according to the Internet of Things (IoT) standards. The proposed platform’s Register Transfer Level (RTL) architecture is entirely developed and designed from scratch using the VHSIC Hardware Description Language (VHDL). The original idea consists of exploiting the nonlinearity of a discretized and optimized 4D Lorenz hyperchaotic system as an encryption keystream generator in a symmetric cryptosystem to secure wireless communicating embedded systems and adapted to the UDP/IP protocol. It was necessary to go through three essential steps to achieve this goal. First, a lightweight and energy-efficient hyperchaos-based encryption IP core is designed, implemented on an FPGA circuit and dedicated to IoT device security, denoted Hyperchaotic-based IoT Device Security Core (HC-IoT-DSC). The designed encryption IP core combines three subsystems: a multiple key size hyperchaotic key generator (HC-KG), a hyperchaotic synchronization by dynamic feedback modulation technique (HCS-DFM), and an online FIPS 140-2-based built-in self-security test (BISST) module. Second, a secure UDP/IP stack is totally implemented using the VHDL language. Third, the proposed architecture was integrated into real-world and real-time secure wireless communication at a distance of 2 km between two delocalized network nodes employing the Xilinx ML605 FPGA platform and the ZigBee E800-DTU module. A panoply of online/offline investigations and experiments were carried out intensely, deeply, and thoroughly to analyze, evaluate and validate the robustness and security aspects of the proposed scheme regarding all the aspects related to embedded system security. Notably, the evaluations were conducted in two phases for all the platform components before and after integrating the proposed security core in real-time wireless communication. The investigations and implementation findings validate that the proposed architecture can attain good performances, and confirm the feasibility of the adopted approach for IoT applications. Furthermore, the timing and power efficiency results present an excellent trade-off between design performance and high-security achievement.

Design and Implementation of an Integrated Management System for Backfill Experimental Data

With the increase in environmental awareness worldwide, the filling mining method has attracted extensive attention because this method can realize safe and green mining in underground metal mines. Recycling waste tailings in stopes to control underground rock movement, and surface settlement can reduce waste environmental pollution while ensuring mining safety. Although many test data are required to support the formulation of the mine backfill scheme, the advanced management tool of backfill test data is insufficient. In this study, a new data management method that is suitable for backfill experiments is proposed. First, this study analyses the main system requirements, including experimental business process modeling, experimental process combing, and a multidimensional query of experimental data. Then, the backfill test business flow and data flow are summarized to establish the backfill test business model and experimental index system. Then, many system functions are designed, including backfill experiment management, experimental data query, backfill knowledge maintenance, and system management. Finally, a backfill test data management system is developed based on B/S architecture. Developing a data interface, having a built‐in test formula and customizing a multidimensional data analysis enable the system to solve the problems in data collection, data accounting, and data analysis. After being put into use in the Backfilling Engineering Laboratory of a group in Shandong, this system improved the data‐sharing rate and utilization rate and provided a convenient data management tool for the laboratory.

Stress-Aware Periodic Test of Interconnects

Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.

A review paper on memory fault models and test algorithms

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM

This investigation proposes a computing-in-memory (CIM) design to circumvent the von Neumann bottleneck which causes limited computation throughput for effective artificial intelligence (AI) applications. The proposed CIM performs multiple operations such as single-instruction basic Boolean operations, addition, and signed number multiplication, and multiple functions such as normal mode and retention mode for the built-in self-test (BIST). Its 2T-Switch requires only two transistors to be utilized for static random-access memory (SRAM) array; thus, the arithmetic unit can be chosen easily and the area overhead is minimized. Its ripple carry adder and multiplier (RCAM) unit based on single-ended disturb-free 7T 1-Kb SRAM was developed using the full swing-gate diffusion input (FS-GDI) technology that has full voltage swing resolution, low power consumption, and less chip area cost. Its Auto-Switching Write Back Circuit restores addition and multiplication operations automatically to assigned memory address. The CIM is implemented using the TSMC 40-nm CMOS process, where the core area is $432.81 \times 510.265\,\,\mu \text{m}^{2}$ . Among the related works, the proposed CIM performs the most number of operations and functions.

Resource-saving current protections for electrical installations with isolated phase busducts

Protections are suggested on the basis of a current relay with two capacitors and a reed switch, which is mounted at a safe distance from a busbar inside the busduct enclosure. The relay does not need in current transformers thus saving copper, steel, and insulating materials. It differs from reed switch based analogs in the noise immunity due to signaling after two actuations of the reed switch; non-operation in the case of sealing (due to the control of duration of breaker contact); the presence of a reed switch fastening structure, and built-in test diagnostics by mean of current supply into the reed switch winding. A technique for selecting protection parameters and assessing their sensitivity is presented. The inductions of magnetic fields which affect the reed switch are calculated with the use of the simplest formulas for the shielding coefficient and of the Bio–Savart–Laplace law, where experimentally derived correcting coefficients are introduced. Examples of the calculation of the induction of protection operation and of reed switch selection are presented along with an oscillogram which confirms the cutoff operability and speed.

Design of a BIST implemented AES crypto-processor ASIC.

This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

Adaptive or embedded software testing and mutation testing

This issue contains four papers. The first paper provides a survey of work on testing adaptive and context-aware systems, while the second one concerns testing embedded systems. The remaining two papers explore particular problems associated with an area well known to most STVR readers: mutation testing. The first paper, ‘Testing of adaptive and context-aware systems: Approaches and challenges’, by Bento R. Siqueira, Fabiano C. Ferrari, Kathiani E. Souza, Valter V. Camargo and Rogério de Lemos, introduces a systematic literature review and a thematic analysis of studies to characterize the state of the art in testing adaptive systems (ASs) and context-aware systems (CASs) and discuss approaches, challenges, observed trends and research limitations and directions. The authors discover recurring research concerns related to AS and CAS testing (such as generation of test cases and built-in tests), recurring testing challenges (such as context monitoring and runtime decisions), some trends (such as model-based testing and hybrid techniques) and some little investigated issues (such as uncertainty and prediction of changes). (Recommended by T.Y. Chen) The second paper, ‘Remote embedded devices test framework on the cloud’, by Il-Seok (Benjamin) Choi and Chang-Sung Jeong, introduces a remote embedded device test framework on the cloud named RED-TFC, whose reliability test manager component can automatically perform various tests for evaluating reliability and performance of distributed shared devices by utilizing the cloud concept. RED-TFC includes two major techniques: the adaptive sample scale for reliability test (ASRT) and the mass sample reliability test (MSRT). The authors analyse two Android smartphone models that include many embedded components and show that RED-TFC can help detect a high number of reliability problems in smartphones. (Recommended by Tanja Vos) The third paper, ‘Analysing the combination of cost reduction techniques in Android mutation testing’, by Macario Polo-Usaola and Isyed Rodríguez-Trujillo, concerns the use of mutation testing when testing mobile apps. As the authors note, when testing an app, one typically deploys the app and its mutants on mobile devices or executes them on an emulator. Doing so increases the test execution time. Naturally, it can also significantly increase the cost of mutation testing, especially when there are many mutants. The authors investigate several techniques that have been devised for reducing execution time in mutation testing and produce a mathematical model with the aim of predicting the time taken when some combination of these techniques is used. (Recommended by Mike Papadakis) The final paper is ‘An ensemble-based predictive mutation testing approach that considers impact of unreached mutants’ by Alireza Aghamohammadi and Seyed-Hassan Mirian-Hosseinabadi. This paper also concerns both mutation testing and prediction. However, the authors look at a different prediction problem: that of predicting whether a mutant will be killed. The authors note that previous work did not consider the impact of unreachable mutants: those where the mutation point is not covered by any of the test cases used. It is argued that since many mutation tools exclude unreachable mutants, such mutants should also be removed from any empirical evaluation. The authors report the results of replicating previous studies but also eliminating unreachable mutants, finding that the resultant performance of prediction techniques is far lower than that reported. The authors then propose an alternative prediction model, which is shown to be effective when unreachable mutants are removed. (Recommended by Tanja Vos)

A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT-LFSR-TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.

Embedded Radiation sensor with OBIST structure for applications in mixed signal systems

Oscillation based testing (OBT) has proven to be a simple and effective test strategy for numerous kind of circuits. In this work, OBT is applied to a radiation sensor to be used as a VLSI cell in embedded applications, implementing an oscillation built-in self-test (OBIST) structure. The oscillation condition is achieved by means of a minimally intrusive switched feedback loop and the response evaluation circuit can be included in a very simple way, minimizing the hardware overhead. The fault simulation indicates a fault coverage of 100% for the circuit under test.Keywords: fault simulation, mixed signal testing, OBIST, oscillation-based test, VLSI testing.