Abstract
Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phase-locked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \!\Sigma $ </tex-math></inline-formula> loop is validated. The entire BIST system consumes 0.6mW with a system self-calibration algorithm to tackle the analog blocks’ nonlinearities.
Highlights
A LL-DIGITAL phase-locked loops (ADPLL) offer extensive re-configurability and require a small area for their loop filter in scaled CMOS [1]–[6]
To overcome the aforementioned drawbacks, we have previously proposed to wrap-around the digital-to-time converter (DTC) in a loop of low hardware complexity, creating a 1st-order to-digital converter (TDC) [1], [29]
To verify the DTC mismatch analysis with a highly accurate measurement, this work improves the precision of the BIST -TDC by reducing the charge pump noise by means of an additional phase/frequency detector (PFD)
Summary
A LL-DIGITAL phase-locked loops (ADPLL) offer extensive re-configurability and require a small area for their (digital) loop filter in scaled CMOS [1]–[6]. The or noise shaping TDCs [18]–[28] can relax the range-linearity trade-off Their gain changes over PVT variations, which is normally calibrated by an on-chip PLL. The conventional TDC architectures, when employed to measure the DTC transfer function, require complex and expensive lab equipment or extra on-chip circuitry to calibrate the gain and mismatch of the TDC itself. To verify the DTC mismatch analysis with a highly accurate measurement, this work improves the precision of the BIST -TDC by reducing the charge pump noise by means of an additional PFD. The vernier TDCs [14], [15] can achieve the sub-gate resolution but they suffer from large mismatchs between the fast and slow paths, and that requires a non-trivial calibration for each delay stage.
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