Built-in Self Research Articles

BIST (Built-In Self Test) Memory by Using VERILOG

Built-In Self-Test (BIST) is a technique that allows a set up to check itself for any error on its own. BIST is a screening mechanism that places the testing functions physically with the circuit applications where system reliability is predominant, and “failure is not an option.” The decision to execute a critical mission must be made only if the complete system is running without any error. BIST structures generate pseudo random combinations and output results for an exclusive circuit under test are compared. BIST can be implemented on entire designs, design blocks or structures within design blocks. Memory is a complex architecture (fabrication wise) and used in a large number of applications. BIST is basically used to help in the testing of memory with the help of a few extra pins. In fact, while testing a memory using BIST, applying a simple clock signal along with a few pins helps test the entire memory IC. The proposed BIST enabled RAM is designed using Verilog

Nonlinear compression block codes: Exact and random search strategy

The nonlinear block codes have significantly better testing abilities than the linear ones used in Built-In Self Test Equipment or test pattern decompressors. Unfortunately, no sufficiently effective deterministic code creation strategy has been discovered till now. This paper deals with a deterministic nonlinear code search strategy and a strategy based on extending linear compression codes by nonlinear check bits that improve the usability of decompressed patterns for testing circuits with more inputs. The earlier works used a purely or partially random search of the nonlinear check-bits truth tables to construct the first nonlinear structures. Here, we derive deterministic rules that can be used for the iterative process of code generation with no necessity of any random search for codes with the number of specified bits equal to three. We compare the code parameters of codes based on linear code extension, direct deterministic code search methods, and previously published results. The most extensive codes still need to be constructed with a partial random search strategy, but keeping the restrictions introduced in the paper causes the search to be substantially more efficient.

Built-In Self Test (BIST) Architecture Simulation for Testing Crosstalk Effects in Array Structured Through Silicon Vias (TSV) in 3DICs

In this research, a BIST (built in self test) architecture for testing crosstalk effects in highly dense Through Silicon Via (TSV) placed in structured array form, in 3DICs (Three Dimensional integrated circuits), designed and simulated using the Xilinx ISE tool and the VHDL language. A novel methodology is proposed, and simulated, to observe the test responses of the victim TSVs in the chosen group simultaneously. Boundary-scan cell structures are modified, created for the purpose of operating in different modes such as shift, update and capture in either conventional serial shift mode as well as in proposed parallel broadcasting mode. Output Response Analyzers (ORA), or signature analyzers that have been simulation-verified. In this study, we suggested a novel encoder-based signature generator to locate faulty TSVs in the parallel-observed TSVs. This paper discusses the whole BIST architecture, the BIST controller built on an algorithmic state machine, the design of TPG (Test Pattern Generator), and the faulty TSV signature generator. Comparing the BIST architecture, to serial shift based interconnect tests done by IEEE 1149.1 (JTAG) such as EXTEST and IEEE 1838 standards, the test’s time complexity of BIST is relatively very low. The entire TSV array test is completed in just 32 clock cycles. The design is adaptable and can be used to broadcast test patterns to a group or to transmit test patterns serially using IEEE 1838 or 1149.1.

Retraction Note to: A saboteur and mutant based built-in self-test and counting threshold-based built-in self repairing mechanism for memories

Retraction Note to: A saboteur and mutant based built-in self-test and counting threshold-based built-in self repairing mechanism for memories

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

This article confirms the advantage of fan-out (FO) packaging in the electrical performance of power delivery among integrated circuit (IC) chips with the best use of land side capacitors (LSCs). On-chip in-place waveform measurements quantitatively evaluate the integrity of powering and signaling within FO wafer level packaging (FOWLP) multiple chip module (MCM) demonstrators, where a pair of IC chips are assembled with LSCs with different sizes and structures. The IC chip incorporates an array of 12 digital cores and on-chip waveform monitor (OCM) circuits. Each digital core consists of a low-voltage differential signaling (LVDS) transceiver channel that is backed by a static random access memory (SRAM)-based built-in self test (BIST) module and supplied by an on-chip voltage regulator module (VRM). The LSCs are placed on the bottom side of an FO interposer and inserted between the output of VRM and the ground plane almost ideally with the shortest length of physical traces. A Si membrane capacitor of 10 nF sustains the lowest power line impedance over the frequency range of 2.0 GHz more constantly than a multilayer ceramic counterpart, and attenuates the high-order harmonic frequency components to the clocking frequency at 750 MHz. The leverage of LSCs in powering also improves signaling and helps achieve the wider eye openings in LVDS channels. The implications are elaborated for the capacitor selections with respect to the physical types of capacitors, the size of capacitances, and the level of shares in power delivery among digital cores, all toward the higher level of integrity in powering and signaling in FOWLP MCMs.

Finite State Machine based Programmable Memory Built-in Self-Test

We propose a methodology to design a Finite State Machine(FSM)-based Programmable Memory Built-In Self Test (PMBIST) which includes a planned procedure for Memory BIST which has a controller to select a test algorithm from a fixed set of algorithms that are built in the memory BIST. In general, it is not possible to test all the different memory modules present in System-on-Chip (SoC) with a single Test algorithm. Subsequently it is desirable to have a programmable Memory BIST controller which can execute multiple test algorithms. The proposed Memory BIST controller is designed as a FSM (Finite State Machine) written in Verilog HDL and this scheme greatly simplifies the testing process and it achieves a good flexibility with smaller circuit size compared with Individual Testing designs. We have used March test algorithms like MATS+, March X, March C- to build the project.

Adjustable PRPG for Low Power Test Patterns

As the power consumption is more in the processes of testing, test vector set compression and controlling of toggling plays a crucial role in reducing the power consumption during test mode. In exploring the controlling techniques of toggling, Pre-Selected Toggling (PRESTO) of test patterns is a technique that can control the toggling of a test patterns in a precise manner in Built-in Self -Test (BIST) architectures. In this paper we modify the architecture of existing Full Version PRESTO that can be used to generate test vectors and in addition binary sequences used as scan chins such that the controlling of sequence of test vectors depends on number of 1’s present in the switch code which is user defined thus reducing the testing time with significant fault coverage, and in addition the optimization is also observed in area and power. The area has decreased by 12.2% and power consumption by 15.43%. The Synthesis and implementation of the architectures are done using Artix7 (xc7a100tcsg324-3) FPGA family. The simulation results have been analyzed through Mentor-graphics Questa-sim 10.7C.

A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC

This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

RETRACTED ARTICLE: A saboteur and mutant based built-in self-test and counting threshold-based built-in self repairing mechanism for memories

In system on chip (SOC) design, memory occupies a large area, if any defects in the memory that will affect the SOC’s total yield. To avoid this, spare rows and columns are added to the memory. When the fault cells need to be operated, spares rows/columns will be used instead of faulty cells using Built-in self-repair (BISR) logic. Repairing logic includes either row repair/column repair or a combination of both. In this paper, we propose two methods, one is on the memory built-in self-test (BIST) for checking the memory array circuit. In the second method, an optimized BISR is employed to repair the faulty memory cells based upon the Built-in redundancy analysis. In the BIST method, our proposed method injects the faults into memory by using two fault injection techniques called saboteurs and mutants with optimized test pattern logic. After the injection of the faults in the memory cell, the fault memory is repaired with the proposed counting threshold algorithm for the BISR scheme. Simulation and synthesis results are obtained using Mentor Graphics and Xilinx ISE Design Suite. From our obtained results it can be inferred that various performance measures like power, area, and timing details are reduced in the proposed methods when compared with the existing exhaustive methods. And this proves that the performance of the overall process is found to be enhanced. Thereby yield can also be enhanced with minimum time to market.

Optimization of Scheduling Technique Rooted on Software Test Routines for Embedded Cores using Quality Factor

Most of the research work to test the fast processors is carried out using external devices as testers;but it was not technically & financially workable. To fulfill the required performance along with providing efficient functionality, an appropriate testingism must be employed by the digital circuits. The best way is to follow testing as an integral part that is self-test. Conventionally large amount of data was stored in an external tester.But there was a difficulty in at speed testing performance using these external hardware. Hence, Built-in-self-test was invented which verifies failure free nature of circuit under test (CUT) with a test mechanism as a part of system itself. It is observed that, if testing of any hardware is carried out with the help of built-in self test, it increases the requirement of additional area and indirectly responsible for forfeits due to degradation in performance.. If a powerful and power optimized core is to be designed, hardware BIST cannot be afforded due to these limitations. To overcome these disadvantages, a new software based BIST techniques is introduced which relies on software test patterns. Here this paper focuses on rooting of software test routines which works using optimization of scheduling and also a Q- factor is proposed to evaluate the nature of proposed method.

Built-in self test of high speed analog-to-digital converters

Signals found in nature need to be converted to the digital domain through analog-to-digital converters (ADCs) to be processed by digital means [1]. For applications in communication and measurement [2], [3], high conversion rates are required. With advances of the complementary metal oxide semiconductor (CMOS) technology, the conversion rates of CMOS ADCs are now well beyond the gigasamples per second (GS/s) range, but only moderate resolutions are required [4]. These ADCs need to be tested after fabrication and, if possible, during field operation. The test costs are a very significant fraction of their production cost [5]. This is mainly due to lengthy use of very expensive automated test equipment (ATE) to apply specific test stimuli to the devices under test (DUT) and to collect and analyze their responses.

An Efficient Fault Detection of FPGA and Memory Using Built-in Self Test [BIST

In this paper, a new technique for localization of fault detection and diagnosis in the interconnects and logic blocks of an arbitrary design implemented on a Field-Programmable Gate Array (FPGA) using BIST is presented. This technique can uniquely identify any single bridging, open or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The test pattern generator and output response analyzer are configured by existing CLBs in FPGAs; thus, no extra area overhead is needed for the proposed BIST structure. The scheme also rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

Specifications of Radio Frequency (RF) analog integrated circuits have increased strictly as their applications tend to be more complicated and high test cost demanding. This makes them very expensive due to an increased test time and to the use of sophisticated test equipment. Alternative test measures, extracted by means of Built-In Self Test (BIST) techniques, are useful approaches to replace standard specification-based tests. One way to evaluate the efficiency of the CUT measures at the design stage is by estimating the Test Escapes (T E ) and the Yield Loss (Y L ) at ppm level. Unfortunately, an important number of Monte Carlo simulations must be run in order to guarantee their accuracy. For certain types of circuits, this requires many months or even years to generate millions of circuits. To overcome this limitation, we present in this paper a new technique where a small number of simulations is sufficient to reach an important precision. This method is based on a classification using machine learning methods, such as SVM and Neural Networks based classifiers to determine pass/fail regions. The proposed approach requires a few number of simulations only to determine the region separating the process parameters generating good and faulty, or pass and fail circuits. Then only this region is needed to estimate the test metrics without running any additional simulation. The proposed methodology is illustrated for the evaluation of a filter BIST technique.

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC.

Fault masking issue on a dependable processor using BIST under highly electromagnetic environment

While power converter and inverter circuits have been enhanced for higher switching speed, higher voltage and higher power density, there are arising problems relating to the effect of near-field noise due to high-current pulse, which can severely affect the operations of the controllers for power converters and the surrounding logic circuits as multi-bit transient faults. A scheme to construct highly reliable processors which measures the noise duration by built-in self test (BIST) and avoids its effect by clock mitigation was proposed in our previous work. However, in some cases, the upper bounds of the noise duration distribution are underestimated due to insufficient testing and fault masking, resulting in faulty operations. In this paper, we further investigate these underestimating situations and then propose a test method to overcome the problem. We use SPICE simulation to evaluate the effectiveness of the proposed scheme.

An FPGA Implementation of On Chip UART Testing with BIST Techniques

A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.

Avalanche Microwave Noise Sources in Commercial 90-nm CMOS Technology

This paper presents a microwave noise source implemented in a commercial CMOS technology. The circuit is based on the avalanche noise generated by both the source-to-bulk and the drain-to-bulk junctions in reverse breakdown. Two sources of different junction area are fabricated using a standard NMOS transistor in 90-nm CMOS technology having a width of 5- and 20- $\mu {\text {m}}$ , respectively. From the experimental characterization emerges that the breakdown voltage of the source/drain to bulk diodes is 12.4 V, whereas excess noise ratios (ENRs) of 20 dB (5- $\mu {\text {m}}$ source) and of 25 dB (20- $\mu {\text {m}}$ source) are observed at 24 GHz for a current density of about 0.14 mA per square micrometer. Finally, a theoretical explanation of the observed behaviors is proposed by means of an equivalent circuit. The developed noise source can be used in a CMOS system-on-chip (SoC) for a variety of applications ranging from the built-in self test (BIST) of the RF chain to the calibration of fully integrated microwave radiometric sensor.

Built-in Self Repair Approach by Module Relocation for FPGA Based Reconfigurable Systems

Systems that are installed in harsh environment conditions are continuously exposed to radiations, temperature variations and pressure variations which cause fast circuit degradation and malfunctioning. FPGAs are used as the core component in many such systems especially in mission critical and safety critical applications. To ensure reliable and prolonged system functioning until mission completion, proper fault recovery techniques need to be incorporated in to the system during the design phase itself. Traditional self-repairing schemes utilize spare cells to replace faulty cells. So, the number of spare cells increases with the number of faults to be repaired which creates high area overhead. Dynamic runtime partial reconfiguration has been considered to be a promising technique that helps improve the flexibility and efficiency of FPGA based systems. The key concept behind self-repairing scheme discussed in this paper is faulty module relocation to enable better use of resources and scheduling of repair for different modules to maintain system operation until mission completion or up to the required lifetime with maximum efficiency. The paper presents an efficient self-repairing scheme for FPGAs which can handle higher number of faults with better resource utilization and lesser overheads.

Window Based Input Vector Monitoring Concurrent BIST Using SRAM Cells with Diagnostic Data Compression

Window based Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the circuit without the requirement to set the circuit offline to perform the test. It is evaluated based on the hardware overhead and the concurrent test latency (CTL). This thesis makes an attempt using novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set of vectors called windows, and the use of a static-RAM like structure. To detect Static Faults in Random Access Memories, proposed a BIST architecture with the capability of hamming syndrome compression. To reduce the diagnostic data volume, a new idea of March element based (MEB)compression is proposed in this BIST Architecture. The data to be diagnosed in a RAM tested with a March test can be efficiently compressed by the MEB compression scheme. The scheme with SRAM cells is shown to perform the detection of error, error location and the error bit position in that location successfully. The software simulation is carried out in ModelSim SE PLUS 6.2b and Xilinx 14.2i design suite. FPGA implementation is done in Xilinx Spartan 3E kit and the output is verified.

Built-In Self Test and Self-Repairing Circuit for Array Multipliers

Background/Objectives: As the size of the chip reduces, nanoscale devices have become more susceptible to manufacturing faults, interference from radiations and transient faults. Many of these errors are not permanent but it causes malfunctioning of circuit either due to the complexity of the circuit or due to the interaction with the software. In this paper, an area and power efficient BIST with self repairing technique has been proposed, which detect and repair the faults in the circuit. Methods/Statistical Analysis: In this research work, a novel Built-In Self-Test (BIST) architecture with self repairing circuit is proposed. The novelty of this architecture is that testing is done along with the self repairing. The Self repairing circuit repairs the fault in the circuit during testing phase itself which increases the reliability of the circuit. Since the insertion of test pattern externally, BIST architecture does not alter the basic multiplier structure. Findings: Average power dissipation of the proposed Built-in self test and self repairing of array multiplier architecture is reduced by 36% since the use of a power efficient test pattern generator. Self repairing has been accomplished by the use of hardware redundancy technique. Also a TMR based self repairing architecture for real time self repairing has been proposed and its area and power dissipation is compared with the other self repairing architecture. Result shows that the BIST with repairing technique is good for low power applications while the TMR based self repairing method is good for real time self repairing applications. The proposed technique can be extended to self repairing processor.