Fault masking issue on a dependable processor using BIST under highly electromagnetic environment

Abstract

While power converter and inverter circuits have been enhanced for higher switching speed, higher voltage and higher power density, there are arising problems relating to the effect of near-field noise due to high-current pulse, which can severely affect the operations of the controllers for power converters and the surrounding logic circuits as multi-bit transient faults. A scheme to construct highly reliable processors which measures the noise duration by built-in self test (BIST) and avoids its effect by clock mitigation was proposed in our previous work. However, in some cases, the upper bounds of the noise duration distribution are underestimated due to insufficient testing and fault masking, resulting in faulty operations. In this paper, we further investigate these underestimating situations and then propose a test method to overcome the problem. We use SPICE simulation to evaluate the effectiveness of the proposed scheme.